AD9834
Rev. B | Page 13 of 32
TERMINOLOGY
Integral Nonlinearity (INL)
Integral nonlinearity is the maximum deviation of any code
from a straight line passing through the endpoints of the
transfer function. The endpoints of the transfer function are zero
scale, a point 0.5 LSB below the first code transition (000 . . . 00 to
000 . . . 01), and full scale, a point 0.5 LSB above the last code
transition (111 . . . 10 to 111 . . . 11). The error is expressed in LSBs.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
and ideal 1 LSB change between two adjacent codes in the DAC.
A specified DNL of ±1 LSB maximum ensures monotonicity.
Output Compliance
The output compliance refers to the maximum voltage that can
be generated at the output of the DAC to meet the specifications.
When voltages greater than that specified for the output com-
pliance are generated, the AD9834 may not meet the
specifications listed in the data sheet.
Spurious-Free Dynamic Range (SFDR)
Along with the frequency of interest, harmonics of the
fundamental frequency and images of these frequencies are
present at the output of a DDS device. The SFDR refers to the
largest spur or harmonic present in the band of interest. The
wideband SFDR gives the magnitude of the largest harmonic or
spur relative to the magnitude of the fundamental frequency in
the 0 to Nyquist bandwidth. The narrow-band SFDR gives the
attenuation of the largest spur or harmonic in a bandwidth of
±200 kHz about the fundamental frequency.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of
harmonics to the rms value of the fundamental. For the
AD9834, THD is defined as
1
65432
V
VVVVV
THD
22222
log20
++++
=
where
V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
, and V
6
are the rms amplitudes of the second harmonic
through the sixth harmonic.
Signal-to-Noise Ratio (SNR)
Signal-to-noise ratio is the ratio of the rms value of the
measured output signal to the rms sum of all other spectral
components below the Nyquist frequency. The value for SNR is
expressed in decibels.
Clock Feedthrough
There is feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
output spectrum of the AD9834.
AD9834
Rev. B | Page 14 of 32
THEORY OF OPERATION
Sine waves are typically thought of in terms of their magnitude
form a(t) = sin (ωt). However, these are nonlinear and not easy
to generate except through piecewise construction. On the
other hand, the angular information is linear in nature, that is,
the phase angle rotates through a fixed angle for each unit of
time. The angular rate depends on the frequency of the signal
by the traditional rate of ω = 2π
f.
MAGNITUDE
PHASE
+1
0
–1
2p
0
2π
4π
6π
2π
4π
6π
02705-025
Figure 27. Sine Wave
Knowing that the phase of a sine wave is linear and given a
reference interval (clock period), the phase rotation for that
period can be determined.
Δ
Phase = ωΔt
Solving for ω
ω = ΔPhaset = 2πf
Solving for f and substituting the reference clock frequency for
the reference period (1/
f
MCLK
= Δt)
f = ΔPhase × f
MCLK
/
The AD9834 builds the output based on this simple equation. A
simple DDS chip can implement this equation with three major
subcircuits: numerically controlled oscillator + phase modulator,
SIN ROM, and digital-to-analog converter. Each of these
subcircuits is discussed in the Circuit Description section.
AD9834
Rev. B | Page 15 of 32
CIRCUIT DESCRIPTION
The AD9834 is a fully integrated direct digital synthesis (DDS)
chip. The chip requires one reference clock, one low precision
resistor, and eight decoupling capacitors to provide digitally created
sine waves up to 37.5 MHz. In addition to the generation of this RF
signal, the chip is fully capable of a broad range of simple and
complex modulation schemes. These modulation schemes are
fully implemented in the digital domain, allowing accurate and
simple realization of complex modulation algorithms using DSP
techniques.
The internal circuitry of the AD9834 consists of the following
main sections: a numerically controlled oscillator (NCO),
frequency and phase modulators, SIN ROM, a digital-to-analog
converter, a comparator, and a regulator.
NUMERICALLY CONTROLLED OSCILLATOR PLUS
PHASE MODULATOR
This consists of two frequency select registers, a phase
accumulator, two phase offset registers, and a phase offset
adder. The main component of the NCO is a 28-bit phase
accumulator. Continuous time signals have a phase range of 0
to 2π. Outside this range of numbers, the sinusoid functions repeat
themselves in a periodic manner. The digital implementation is no
different. The accumulator simply scales the range of phase
numbers into a multibit digital word. The phase accumulator in
the AD9834 is implemented with 28 bits. Therefore, in the
AD9834, 2π = 2
28
. Likewise, the ΔPhase term is scaled into this
range of numbers:
0 < Δ
Phase < 2
28
− 1.
Making these substitutions into the equation above
f = ΔPhase × f
MCLK
/2
28
where 0 < Δ
Phase < 2
28
− 1.
The input to the phase accumulator can be selected either from
the FREQ0 register or FREQ1 register, and is controlled by the
FSELECT pin or the FSEL bit. NCOs inherently generate con-
tinuous phase signals, thus avoiding any output discontinuity
when switching between frequencies.
Following the NCO, a phase offset can be added to perform
phase modulation using the 12-bit phase registers. The contents
of one of these phase registers is added to the MSBs of the NCO.
The AD9834 has two phase registers, the resolution of these
registers being 2π/4096.
SIN ROM
To make the output from the NCO useful, it must be converted
from phase information into a sinusoidal value. Phase informa-
tion maps directly into amplitude; therefore, the SIN ROM uses
the digital phase information as an address to a look-up table
and converts the phase information into amplitude.
Although the NCO contains a 28-bit phase accumulator, the
output of the NCO is truncated to 12 bits. Using the full resolu-
tion of the phase accumulator is impractical and unnecessary
because it requires a look-up table of 2
28
entries. It is necessary
only to have sufficient phase resolution such that the errors due
to truncation are smaller than the resolution of the 10-bit DAC.
This requires the SIN ROM to have two bits of phase resolution
more than the 10-bit DAC.
The SIN ROM is enabled using the OPBITEN and MODE bits
in the control register. This is explained further in Table 18.
DIGITAL-TO-ANALOG CONVERTER
The AD9834 includes a high impedance current source 10-bit
DAC capable of driving a wide range of loads. The full-scale
output current can be adjusted for optimum power and external
load requirements using a single external resistor (R
SET
).
The DAC can be configured for either single-ended or differential
operation. IOUT and IOUTB can be connected through equal
external resistors to AGND to develop complementary output
voltages. The load resistors can be any value required, as long as
the full-scale voltage developed across it does not exceed the
voltage compliance range. Since full-scale current is controlled
by R
SET
, adjustments to R
SET
can balance changes made to the
load resistors.
COMPARATOR
The AD9834 can be used to generate synthesized digital clock
signals. This is accomplished by using the on-board self-biasing
comparator that converts the sinusoidal signal of the DAC to a
square wave. The output from the DAC can be filtered externally
before being applied to the comparator input. The comparator
reference voltage is the time average of the signal applied to V
IN
.
The comparator can accept signals in the range of approximately
100 mV p-p to 1 V p-p. As the comparator input is ac-coupled, to
operate correctly as a zero crossing detector, it requires a minimum
input frequency of typically 3 MHz. The comparator output is a
square wave with an amplitude from 0 V to DVDD.

AD9834BRU-REEL

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Data Acquisition ADCs/DACs - Specialized 20mW Power 2.3-5.5V 75MHz
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