AD9834
Rev. B | Page 4 of 32
Grade B, Grade C
1
Parameter
2
Min Typ Max Unit Test Conditions/Comments
I
DD
6
B Grade 2.0 3 mA I
DD
code dependent (see Figure 9)
C Grade 2.7 3.7 mA I
DD
code dependent (see Figure 9)
I
AA
+ I
DD
6
B Grade 5.8 8 mA
C Grade 6.5 8.7 mA
Low Power Sleep Mode
B Grade 0.5 mA DAC powered down, MCLK running
C Grade 0.6 mA DAC powered down, MCLK running
1
B grade: MCLK = 50 MHz; C grade: MCLK = 75 MHz. For specifications that do not specify a grade, the value applies to both grades.
2
Operating temperature range is as follows: B, C versions: −40°C to +105°C, typical specifications are at 25°C.
3
For compliance, with specified load of 200 Ω, I
OUT
full scale should not exceed 4 mA.
4
Guaranteed by design.
5
Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current.
6
Measured with the digital inputs static and equal to 0 V or DVDD.
R
SET
6.8k
IOUT
12
10-BIT DAC
20pF
FS ADJUST
AD9834
REGULATOR
100n
F
CAP/2.5V
10nF
REFOUT
COMP
10nF
AVDD
SIN
ROM
R
LOAD
200
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
02705-002
Figure 2. Test Circuit Used to Test the Specifications
AD9834
Rev. B | Page 5 of 32
TIMING CHARACTERISTICS
DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter
1
Limit at T
MIN
to T
MAX
Unit Test Conditions/Comments
t
1
20/13.33 ns min MCLK period: 50 MHz/75 MHz
t
2
8/6 ns min MCLK high duration: 50 MHz/75 MHz
t
3
8/6 ns min MCLK low duration: 50 MHz/75 MHz
t
4
25 ns min SCLK period
t
5
10 ns min SCLK high duration
t
6
10 ns min SCLK low duration
t
7
5 ns min FSYNC to SCLK falling edge setup time
t
8 MIN
10 ns min FSYNC to SCLK hold time
t
8 MAX
t
4
− 5 ns max
t
9
5 ns min Data setup time
t
10
3 ns min Data hold time
t
11
8 ns min FSELECT, PSELECT setup time before MCLK rising edge
t
11A
8 ns min FSELECT, PSELECT setup time after MCLK rising edge
t
12
5 ns min SCLK high to FSYNC falling edge setup time
1
Guaranteed by design, not production tested.
Timing Diagrams
MCLK
t
1
t
3
t
2
02705-003
Figure 3. Master Clock
FSELECT,
PSELECT
VALID DATA VALID DATA VALID DATA
MCLK
t
11A
t
11
02705-004
Figure 4. Control Timing
D0
SCLK
FSYNC
SDATA
D15 D14 D2 D1 D15 D14
t
12
t
7
t
6
t
8
t
5
t
4
t
9
t
10
02705-005
Figure 5. Serial Timing
AD9834
Rev. B | Page 6 of 32
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 3.
Parameter Ratings
AVDD to AGND −0.3 V to +6 V
DVDD to DGND −0.3 V to +6 V
AVDD to DVDD −0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
CAP/2.5V +2.75 V
Digital I/O Voltage to DGND −0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND −0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
TSSOP Package
θ
JA
Thermal Impedance 143°C/W
θ
JC
Thermal Impedance 45°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature 220°C
Reflow Soldering (Pb-Free)
Peak Temperature 260°C (+0/–5)
Time at Peak Temperature 10 sec to 40 sec
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

AD9834BRU-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized 20mW Power 2.3-5.5V 75MHz
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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