AD9834BRU-REEL Datasheet USB2513-AEZG, USB2514-AEZG, AD9834BRU-REEL | P19-P21

AD9834

Rev. B | Page 19 of 32

Bit Name Description

DB5 OPBITEN

The function of this bit is to control whether there is an output at the SIGN BIT OUT pin. This bit should remain at 0 if the

user is not using the SIGN BIT OUT pin.

OPBITEN = 1 enables the SIGN BIT OUT pin.

OPBITEN = 0, the SIGN BIT OUT output buffer is put into a high impedance state, therefore no output is available at

the SIGN BIT OUT pin.

DB4 SIGN/PIB The function of this bit is to control what is output at the SIGN BIT OUT pin.

SIGNPIB = 1, the on-board comparator is connected to SIGN BIT OUT. After filtering the sinusoidal output from the

DAC, the waveform can be applied to the comparator to generate a square waveform. Refer to Table 17.

SIGNPIB = 0, the MSB (or MSB/2) of the DAC data is connected to the SIGN BIT OUT pin. Bit DIV2 controls whether it

is the MSB or MSB/2 that is output.

DB3 DIV2 DIV2 is used in association with SIGNPIB and OPBITEN. Refer to Table 17.

DIV2 = 1, the digital output is passed directly to the SIGN BIT OUT pin.

DIV2 = 0, the digital output/2 is passed directly to the SIGN BIT OUT pin.

DB2 Reserved This bit must always be set to 0.

DB1 MODE

The function of this bit is to control what is output at the IOUT pin/IOUTB pin. This bit should be set to 0 if the Control

Bit OPBITEN = 1.

MODE = 1, the SIN ROM is bypassed, resulting in a triangle output from the DAC.

MODE = 0, the SIN ROM is used to convert the phase information into amplitude information, resulting in a

sinusoidal signal at the output. See Table 18.

DB0 Reserved This bit must always be set to 0.

FREQUENCY AND PHASE REGISTERS

The AD9834 contains two frequency registers and two phase

registers. These are described in Table 7.

Table 7. Frequency/Phase Registers

FREQ0 28 bits

Frequency Register 0. When either the

FSEL bit or FSELECT pin = 0, this register

defines the output frequency as a fraction

of the MCLK frequency.

FREQ1 28 bits

Frequency Register 1. When either the

FSEL bit or FSELECT pin = 1, this register

defines the output frequency as a fraction

of the MCLK frequency.

PHASE0 12 bits

Phase Offset Register 0. When either the

PSEL bit or PSELECT pin = 0, the contents

of this register are added to the output of

the phase accumulator.

PHASE1 12 bits

Phase Offset Register 1. When either the

PSEL bit or PSELECT pin = 1, the contents

of this register are added to the output of

the phase accumulator.

The analog output from the AD9834 is

MCLK

× FREQREG

where

FREQREG is the value loaded into the selected frequency

2π/4096 ×

PHASEREG

where

PHASEREG is the value contained in the selected phase

selected output frequency and the reference clock frequency to

avoid unwanted output anomalies.

Access to the frequency and phase registers is controlled by

both the FSELECT and PSELECT pins, and the FSEL and PSEL

control bits. If the Control Bit PIN/SW = 1, the pins control the

function; whereas, if PIN/SW = 0, the bits control the function.

This is outlined in Tabl e 8 and Table 9. If the FSEL and PSEL

bits are used, the pins should be held at CMOS logic high or

low. Control of the frequency/phase registers is interchangeable

from the pins to the bits.

Table 8. Selecting a Frequency Register

FSELECT FSEL PIN/SW Selected Register

0 X 1 FREQ0 REG

1 X 1 FREQ1 REG

X 0 0 FREQ0 REG

X 1 0 FREQ1 REG

Table 9. Selecting a Phase Register

PSELECT PSEL PIN/SW Selected Register

0 X 1 PHASE0 REG

1 X 1 PHASE1 REG

X 0 0 PHASE0 REG

X 1 0 PHASE1 REG

The FSELECT pin and PSELECT pin are sampled on the internal

falling edge of MCLK. It is recommended that the data on these

pins does not change within a time window of the falling edge of

MCLK (see Figure 4 for timing). If FSELECT or PSELECT changes

value when a falling edge occurs, there is an uncertainty of one

MCLK cycle as it pertains to when control is transferred to the

other frequency/phase register.

The flow charts in Figure 32 and Figure 33 show the routine

for selecting and writing to the frequency and phase registers of

the AD9834.

AD9834

Rev. B | Page 20 of 32

WRITING TO A FREQUENCY REGISTER

When writing to a frequency register, Bit DB15 and Bit DB14

give the address of the frequency register.

Table 10. Frequency Register Bits

DB15 DB14 DB13 . . . DB0

0 1 14 FREQ0 REG BITS

1 0 14 FREQ1 REG BITS

If the user wants to alter the entire contents of a frequency

performed because the frequency registers are 28 bits wide. The

first write contains the 14 LSBs, and the second write contains

the 14 MSBs. For this mode of operation, Control Bit B28

(DB13) should be set to 1. An example of a 28-bit write is

shown in Table 11.

Note however, that continuous writes to the same frequency

updates during the writes. If a frequency sweep, or something

similar, is required, it is recommended that users alternate

between the two frequency registers.

Table 11. Writing FFFC000 to FREQ0 REG

SDATA Input Result of Input Word

0010 0000 0000 0000

Control word write

(DB15, DB14 = 00), B28 (DB13) = 1,

HLB (DB12) = X

0100 0000 0000 0000

FREQ0 REG write

(DB15, DB14 = 01), 14 LSBs = 0000

0111 1111 1111 1111

FREQ0 REG write (DB15, DB14 = 01),

14 MSBs = 3FFF

In some applications, the user does not need to alter all 28 bits

of the frequency register. With coarse tuning, only the 14 MSBs

are altered; though with fine tuning only the 14 LSBs are altered.

By setting Control Bit B28 (DB13) to 0, the 28-bit frequency

14 MSBs and the other containing the 14 LSBs. This means that

the 14 MSBs of the frequency word can be altered independent

of the 14 LSBs, and vice versa. Bit HLB (DB12) in the control

this are shown in Table 12 and Tabl e 13.

Table 12. Writing 3FFF to the 14 LSBs of FREQ1 REG

SDATA Input Result of Input Word

0000 0000 0000 0000

Control word write

(DB15, DB14 = 00), B28 (DB13) = 0,

HLB (DB12) = 0, that is, LSBs

1011 1111 1111 1111

FREQ1 REG write

(DB15, DB14 = 10), 14 LSBs = 3FFF

Table 13. Writing 00FF to the 14 MSBs of FREQ0 REG

SDATA Input Result of Input Word

0001 0000 0000 0000

Control word write

(DB15, DB14 = 00), B28 (DB13) = 0,

HLB (DB12) = 1, that is, MSBs

0100 0000 1111 1111

FREQ0 REG write

(DB15, DB14 = 01), 14 MSBs = 00FF

WRITING TO A PHASE REGISTER

When writing to a phase register, Bit DB15 and Bit DB14 are set

to 11. Bit DB13 identifies which phase register is being loaded.

Table 14. Phase Register Bits

DB15 DB14 DB13 DB12 DB11 DB0

1 1 0 X MSB 12 PHASE0 bits LSB

1 1 1 X MSB 12 PHASE1 bits LSB

RESET FUNCTION

The RESET function resets appropriate internal registers to 0 to

provide an analog output of midscale. RESET does not reset the

phase, frequency, or control registers.

When the AD9834 is powered up, the part should be reset. To

reset the AD9834, set the RESET pin/bit to 1. To take the part

out of reset, set the pin/bit to 0. A signal appears at the DAC

output seven MCLK cycles after RESET is set to 0.

The RESET function is controlled by both the RESET pin and

the RESET control bit. If the Control Bit PIN/SW = 0, the

RESET bit controls the function, whereas if PIN/SW = 1, the

RESET pin controls the function.

Table 15. Applying RESET

RESET Pin RESET Bit PIN/SW Bit Result

0 X 1 No reset applied

1 X 1 Internal registers reset

X 0 0 No reset applied

X 1 0 Internal registers reset

The effect of asserting the RESET pin is evident immediately at

the output, that is, the zero-to-one transition of this pin is not

sampled. However, the negative transition of RESET is sampled

on the internal falling edge of MCLK.

SLEEP FUNCTION

Sections of the AD9834 that are not in use can be powered

down to minimize power consumption by using the SLEEP

function. The parts of the chip that can be powered down are

the internal clock and the DAC. The DAC can be powered

down through hardware or software. The pin/bits required for

the SLEEP function are outlined in Table 16.

AD9834

Rev. B | Page 21 of 32

Table 16. Applying the SLEEP Function

SLEEP

SLEEP1

Bit

SLEEP12

Bit

PIN/SW

Bit

Result

0 X X 1 No power-down

1 X X 1

DAC powered

down

X 0 0 0 No power-down

X 0 1 0

DAC powered

down

X 1 0 0

Internal clock

disabled

X 1 1 0

Both the DAC

powered down

and the internal

clock disabled

DAC Powered Down

This is useful when the AD9834 is used to output the MSB of

the DAC data only. In this case, the DAC is not required and

can be powered down to reduce power consumption.

Internal Clock Disabled

When the internal clock of the AD9834 is disabled, the DAC

output remains at its present value because the NCO is no

longer accumulating. New frequency, phase, and control words

can be written to the part when the SLEEP1 control bit is active.

The synchronizing clock remains active, meaning that the

selected frequency and phase registers can also be changed

either at the pins or by using the control bits. Setting the

SLEEP1 bit to 0 enables the MCLK. Any changes made to the

registers when SLEEP1 is active are observed at the output after

a certain latency.

The effect of asserting the SLEEP pin is evident immediately at

the output, that is, the zero-to-one transition of this pin is not

sampled. However, the negative transition of SLEEP is sampled

on the internal falling edge of MCLK.

SIGN BIT OUT PIN

The AD9834 offers a variety of outputs from the chip. The

digital outputs are available from the SIGN BIT OUT pin. The

available outputs are the comparator output or the MSB of the

DAC data. The bits controlling the SIGN BIT OUT pin are

outlined in Table 17.

This pin must be enabled before use. The enabling/disabling of

this pin is controlled by the Bit OPBITEN (DB5) in the control

MODE bit (DB1) in the control register should be set to 0 if

OPBITEN = 1.

Comparator Output

The AD9834 has an on-board comparator. To connect this

comparator to the SIGN BIT OUT pin, the SIGNPIB (DB4)

control bit must be set to 1. After filtering the sinusoidal output

from the DAC, the waveform can be applied to the comparator

to generate a square waveform.

MSB from the NCO

The MSB from the NCO can be output from the AD9834. By

setting the SIGNPIB (DB4) control bit to 0, the MSB of the

DAC data is available at the SIGN BIT OUT pin. This is useful

as a coarse clock source. This square wave can also be divided

by two before being output. Bit DIV2 (DB3) in the control register

controls the frequency of this output from the SIGN BIT OUT pin.

Table 17. Various Outputs from SIGN BIT OUT

OPBITEN

Bit

MODE

Bit

SIGN/PIB

Bit

DIV2

Bit

SIGN BIT OUT Pin

0 X X X High impedance

1 0 0 0 DAC data MSB/2

1 0 0 1 DAC data MSB

1 0 1 0 Reserved

1 0 1 1 Comparator output

1 1 X X Reserved

THE IOUT AND IOUTB PINS

The analog outputs from the AD9834 are available from the

IOUT and IOUTB pins. The available outputs are a sinusoidal

output or a triangle output.

Sinusoidal Output

The SIN ROM converts the phase information from the

frequency and phase registers into amplitude information,

resulting in a sinusoidal signal at the output. To have a

sinusoidal output from the IOUT and IOUTB pins, set

Bit MODE (DB1) to 0.

Triangle Output

The SIN ROM can be bypassed so that the truncated digital

output from the NCO is sent to the DAC. In this case, the

output is no longer sinusoidal. The DAC produces 10-bit linear

triangular function. To have a triangle output from the IOUT

and IOUTB pins, set Bit MODE (DB1) to 1.

Note that the SLEEP pin and SLEEP12 bit must be 0 (that is, the

DAC is enabled) when using the IOUT and IOUTB pins.

Table 18. Various Outputs from IOUT and IOUTB

OPBITEN Bit MODE Bit IOUT and IOUTB Pins

0 0 Sinusoid

0 1 Triangle

1 0 Sinusoid

1 1 Reserved

3π/2 7π/2 11π/2

OUT MAX

OUT MIN

2705-027

Figure 30. Triangle Output

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

AD9834BRU-REEL

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Data Acquisition ADCs/DACs - Specialized 20mW Power 2.3-5.5V 75MHz

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