AD9834
Rev. B | Page 25 of 32
GROUNDING AND LAYOUT
The printed circuit board that houses the AD9834 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can easily be separated. A minimum
etch technique is generally best for ground planes because it
gives the best shielding. Digital and analog ground planes
should only be joined in one place. If the AD9834 is the only
device requiring an AGND to DGND connection, the ground
planes should be connected at the AGND and DGND pins of
the AD9834. If the AD9834 is in a system where multiple
devices require AGND to DGND connections, the connection
should be made at one point only, establishing a star ground
point as close as possible to the AD9834.
Avoid running digital lines under the device because these
couple noise onto the die. The analog ground plane should be
allowed to run under the AD9834 to avoid noise coupling. The
power supply lines to the AD9834 should use as large a track as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals, such
as clocks, should be shielded with digital ground to avoid
radiating noise to other sections of the board. Avoid crossover
of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other to reduce the
effects of feedthrough through the board. A microstrip
technique is by far the best, but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes and signals are placed
on the other side.
Good decoupling is important. The analog and digital supplies
to the AD9834 are independent and separately pinned out to
minimize coupling between analog and digital sections of the
device. All analog and digital supplies should be decoupled to
AGND and DGND, respectively, with 0.1 μF ceramic capacitors
in parallel with 10 μF tantalum capacitors. To achieve the best
performance from the decoupling capacitors, they should be
placed as close as possible to the device, ideally right up against
the device. In systems where a common supply is used to drive
both the AVDD and DVDD of the AD9834, it is recommended
that the systems AVDD supply be used. This supply should have
the recommended analog supply decoupling between the
AVDD pins of the AD9834 and AGND, and the recommended
digital supply decoupling capacitors between the DVDD pins
and DGND.
Proper operation of the comparator requires good layout
strategy. The strategy must minimize the parasitic capacitance
between V
IN
and the SIGN BIT OUT pin by adding isolation
using a ground plane. For example, in a multilayered board, the
V
IN
signal could be connected to the top layer and the SIGN
BIT OUT connected to the bottom layer, so that isolation is
provided by the power and ground planes between them.
AD9834
Rev. B | Page 26 of 32
INTERFACING TO MICROPROCESSORS
The AD9834 has a standard serial interface that allows the part
to interface directly with several microprocessors. The device
uses an external serial clock to write the data/control information
into the device. The serial clock can have a frequency of 40 MHz
maximum. The serial clock can be continuous, or it can idle high
or low between write operations. When data/control information is
being written to the AD9834, FSYNC is taken low and is held
low until the 16 bits of data are written into the AD9834. The
FSYNC signal frames the 16 bits of information being loaded
into the AD9834.
AD9834 TO ADSP-21xx INTERFACE
Figure 35 shows the serial interface between the AD9834 and
the ADSP-21xx. The ADSP-21xx should be set up to operate in
the SPORT transmit alternate framing mode (TFSW = 1). The
ADSP-21xx is programmed through the SPORT control register
and should be configured as follows:
Internal clock operation (ISCLK = 1)
Active low framing (INVTFS = 1)
16-bit word length (SLEN = 15)
Internal frame sync signal (ITFS = 1)
Generate a frame sync for each write (TFSR = 1)
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. The data is clocked out on
each rising edge of the serial clock and clocked into the AD9834
on the SCLK falling edge.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD9834
1
FSYNC
SDATA
SCLK
TFS
DT
SCLK
ADSP-21xx
1
02705-032
Figure 35. ADSP-21xx to AD9834 Interface
AD9834 TO 68HC11/68L11 INTERFACE
Figure 36 shows the serial interface between the AD9834 and
the 68HC11/68L11 microcontroller. The microcontroller is
configured as the master by setting Bit MSTR in the SPCR to 1,
providing a serial clock on SCK while the MOSI output drives
the serial data line SDATA. Because the microcontroller does
not have a dedicated frame sync pin, the FSYNC signal is
derived from a port line (PC7). The setup conditions for correct
operation of the interface are as follows:
SCK idles high between write operations (CPOL = 0)
Data is valid on the SCK falling edge (CPHA = 1)
When data is being transmitted to the AD9834, the FSYNC line is
taken low (PC7). Serial data from the 68HC11/68L11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. In order to load
data into the AD9834, PC7 is held low after the first eight bits are
transferred and a second serial write operation is performed to the
AD9834. Only after the second eight bits have been transferred
should FSYNC be taken high again.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD9834
1
FSYNC
SDATA
SCLK
68HC11/68L11
1
PC7
MOSI
SCK
02705-033
Figure 36. 68HC11/68L11 to AD9834 Interface
AD9834
Rev. B | Page 27 of 32
AD9834 TO 80C51/80L51 INTERFACE
Figure 37 shows the serial interface between the AD9834 and
the 80C51/80L51 microcontroller. The microcontroller is
operated in Mode 0 so that TXD of the 80C51/80L51 drives SCLK
of the AD9834, and RXD drives the serial data line (SDATA). The
FSYNC signal is derived from a bit programmable pin on the port
(P3.3 is shown in the diagram). When data is to be transmitted to
the AD9834, P3.3 is taken low. The 80C51/80L51 transmits data
in 8-bit bytes, thus only eight falling SCLK edges occur in each
cycle. To load the remaining eight bits to the AD9834, P3.3 is
held low after the first eight bits have been transmitted, and a
second write operation is initiated to transmit the second byte of
data. P3.3 is taken high following the completion of the second
write operation. SCLK should idle high between the two write
operations. The 80C51/80L51 outputs the serial data in an LSB-
first format. The AD9834 accepts the MSB first (the four MSBs
being the control information, the next four bits being the
address, and the eight LSBs containing the data when writing to
a destination register). Therefore, the transmit routine of the
80C51/80L51 must take this into account and rearrange the bits
so that the MSB is output first.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD9834
1
FSYNC
SDATA
SCLK
80C51/80L51
1
P3.3
RXD
TXD
02705-034
Figure 37. 80C51/80L51 to AD9834 Interface
AD9834 TO DSP56002 INTERFACE
Figure 38 shows the interface between the AD9834 and the
DSP56002. The DSP56002 is configured for normal mode
asynchronous operation with a gated internal clock (SYN = 0,
GCK = 1, SCKD = 1). The frame sync pin is generated internally
(SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and
the frame sync signal frames the 16 bits (FSL = 0). The frame sync
signal is available on Pin SC2, but needs to be inverted before
being applied to the AD9834. The interface to the DSP56000/
DSP56001 is similar to that of the DSP56002.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD9834
1
FSYNC
SDATA
SCLK
DSP56002
1
SC2
STD
SCK
02705-035
Figure 38. DSP56002 to AD9834 Interface

AD9834BRU-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized 20mW Power 2.3-5.5V 75MHz
Lifecycle:
New from this manufacturer.
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