Philips Semiconductors Product data
PCA9504AGlue chip 4
2004 May 11
21
SW00591
A20M*
GPO_FLUSH_CACHE*
INIT*
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
INIT_OUT*
tt
t1
t
t1
t1
Figure 12. Waveforms for Case 7
SW00592
A20M*
GPO_FLUSH_CACHE*
INIT*
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
INIT_OUT*
tt
t1
t1
Figure 13. Waveforms for boundary GPO_FLUSH_CACHE* Case
• Timings should remain the same for both a 66 MHz or 33 MHz
CLK_IN input.
• The boundary condition for INIT listed above, is a special case
where immediately following the FLUSH_OUT*, INIT_OUT* cycle,
the ICH2 asserts INIT* into the Glue Chip.
• The boundary condition for GPO_FLUSH_CACHE* listed above,
is a special case where immediately following the first assertion of
GPO_FLUSH_CACHE*, the GPO is de-asserted, then re-asserted
again before the timings have had a chance to complete.
NOTE:
1. Nominal timing values with tolerances are listed in the DC
Characteristics table.
GPO_FLUSH_CACHE* – input to logic, GPO from the ICH2,
programmed active LOW.
INIT* – input to logic, INIT* signal from the ICH2.
A20M* – input to logic, A20M* signal from the ICH2.
FLUSH_OUT_CPU* – output of logic, route to CPU FLUSH* pin.
FLUSH_OUT_CPU* – output of logic, routed to FWH INIT* pin.
INIT_OUT* – output of logic, routed to CPU INIT* pin.
