Philips Semiconductors Product data
PCA9504AGlue chip 4
2004 May 11
22
SW00593
LATCHED_BACKFEED_CUT
BACKFEED_CUT*
SLP_S5*
T1
T2
Figure 14. Power up signal sequencing
Power up signal sequencing is shown in Figure 14. BACKFEED_CUT* is following the power rail up to its final value.
LATCHED_BACKFEED_CUT should stay LOW, never turning on. SLP_S5* goes to its HIGH value when the power rails have stabilized,
25 msec after power on. BACKFEED_CUT* is pulled LOW a period T1 after SLP_S5* goes HIGH. T1 can be as short as 1msec. Typical
measured values are 200 msec. T1 and T2 are guaranteed by the inherent design of the system and are not controlled by Glue Chip.
SW00594
LATCHED_BACKFEED_CUT
BACKFEED_CUT*
Tpropr
Tr
Tpropf
Tf
SLP_S5*
Figure 15. 1st sequence timing
The first possible sequence is with SLP_S5*staying HIGH and BACKFEED_CUT* transitioning from LOW to HIGH, remaining HIGH for an
undetermined period and then going back to LOW and the system is back at the end of the power-up sequence. The power-up sequence is
shown in Figure 15. During these BACKFEED_CUT* transitions, the propagation delays, rise and fall times, and going into regulation times
LATCHED_BACKFEED_CUT are as described in Figure 16. The first sequence starts can start at the end of the power-up sequence at any time.
SW00595
LATCHED_BACKFEED_CUT
BACKFEED_CUT*
T3
Tpropf
SLP_S5*
Tpropr
Tr
Tf
T4
Figure 16. 2nd sequence timing
Signal sequencing for the second possible sequence is shown in Figure 16. BACKFEED_CUT* goes from LOW to HIGH and SLP_S5* goes
from HIGH to LOW, 30 µsec to 65 µsec (T3) later. LATCHED_BACKFEED_CUT goes HIGH when BACKFEED_CUT* goes HIGH and then
LATCHED_BACKFEED_CUT returns to LOW when SLP_S5* goes LOW. BACKFEED_CUT* stays HIGH and SLP_S5* stays LOW for an
indeterminate time and then SLP_S5* will go HIGH. A minimum of 1msec (T4) later, BACKFEED_CUT* will go LOW and the system is back at
the end of the power-up sequence. Typical measured values of T4 are 250 msec. During all transitions, the propagation delays, rise and fall
times, and going into regulation times for LATCHED_BACKFEED_CUT are as described in Figure 16. The first sequence starts can start at the
end of the power-up sequence at any time.
Philips Semiconductors Product data
PCA9504AGlue chip 4
2004 May 11
23
RSMRST* GENERATION
RSMRST* is a delayed 3.3 V hysteresis copy of V_5PO_STBY. RSMRST* is delayed going inactive from the rising edge of V_5PO_STBY by
32 ms, nominal. This delay starts when V_5PO_STBY hits the trip point. There is minimal delay on the falling edge.
SW00596
V_5P0_STBY
RSMRST*
max
min
V
TRIP
t
reset
Figure 17. Resume reset functionality
SW00597
t
RESET
t
RESET_FALL
V_5P0_STBY
RSMRST*
Figure 18. Resume reset functionality during brown out
Philips Semiconductors Product data
PCA9504AGlue chip 4
2004 May 11
24
AUDIO-DISABLE
AUD_EN PCIRST AUD_RST
0 0 0
0 1 0
1 0 0
1 1 1
MUTE AUDIO CIRCUIT
MUTE_AUD AUD_SHDN
0 1
1 0
HD SINGLE COLOR LED DRIVER
PRIMARY_HD SECONDARY_HD SCSI HD_LED
0 0 0 0
0 X X 0
X 0 X 0
X X 0 0
1 1 1 HI–Z
IDE RESET SIGNAL GENERATION AND PCRIST DRIVE STRENGTH
PCIRST IDE_RSTDRV
1
PCIRST_OUT
0 0 0
1 1 1
NOTE:
1. IDE_RSTDRV is a 5 V copy of PCIRST. PCIRST_OUT is a 3.3 V copy of PCIRST.
PWRGD SIGNAL GENERATION
FPRST PWRGD_PS PWRGD_3V
0 0 0
0 1 0
1 0 0
1 1 1
FLUSH_OUT / INIT_OUT CIRCUIT
CASE A20M GPO_FLUSH_CACHE INIT FLUSH_OUT_CPU FLUSH_OUT_FWH INIT_OUT
1 1 Falling edge 0 0(for t1) 0(for t1) 0, Hi-Z, then 0 (delayed by
t1-t, then active for 2*t)
2 1 Falling edge 1 0(for t1) 0(for t1) Hi-Z, 0 (delayed by t1-t,
then active for 2*t)
3 X 1 0 Hi-Z Hi-Z 0
4 X 1 1 Hi-Z Hi-Z Hi-Z
5 0 Falling edge 1 Hi-Z Hi-Z Hi-Z
6 0 Falling edge 0 Hi-Z Hi-Z 0
CLK_IN AND SEL_33_66
SEL_33_66 CLK_IN RATE
0 66 MHz
1 33 MHz

PCA9504ADGG,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC GLUE CHIP 4 DUAL 56TSSOP
Lifecycle:
New from this manufacturer.
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