NB3L202K
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13
Signal and Feature Operation
Table 7. OE# FUNCTIONALITY
(Notes 41, 42 and 43)
CLK_IN / CLK_IN# OE# (Pin) DIF DIF # Notes
Running 1 Low Low 41
Running 0 Running Running
Not Running x x x
41.The outputs are tri−stated, but the termination networks pull them low
42.OE# pins are asynchronous asserted−low signals.
43.Each OE# pin controls two pair of DIF outputs.
OE# Assertion (Transition from ‘1’ to ‘0’)
All differential outputs that were tri−stated (low due to
termination pull down) will resume normal operation in a
glitch free manner. The latency from the assertion to active
outputs is 4 − 12 DIF clock periods.
Note: Input clock must remain running for a minimum of
12 clock cycles.
OE# De−Assertion (Transition from ‘0’ to ‘1’)
The maximum latency from the de−assertion to tristated
(low due to termination pull down) outputs is 12 DIF clock
periods.
Table 8. NB3L202K RESISTIVE LUMPED TEST LOADS FOR DIFFERENTIAL CLOCKS
Board Target Trace/Term Z Reference R, Iref = VDD/(3*R
REF
) Output Current V
OH
@ Z Rs Rp
100 W Differential
50 W Single−Ended
R
REF
= 475 W 1%,
I
REF
= 2.32 mA
I
OH
= 6 * I
REF
0.7 V @ 50
33 W
5%
50 W
5%
85 W Differential
43 W Single−Ended
R
REF
= 412 W, 1%,
I
REF
= 2.67 mA
I
OH
= 6 * I
REF
0.7V @ 43.2
27 W
5%
43 W
5%
ORDERING INFORMATION
Device Package Shipping
NB3L202KMNG QFN16
(Pb−Free)
123 Units / Rail
NB3L202KMNTXG QFN16
(Pb−Free)
3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NB3L202K
www.onsemi.com
14
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485AE
ISSUE B
16X
SEATING
PLANE
L
D
E
0.15 C
A
A1
e
D2
E2
b
1
4
58
12
9
16 13
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. OUTLINE MEETS JEDEC DIMENSIONS PER
MO−220, VARIATION VEED−6.
B
A
0.15
C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN 1
LOCATION
0.10 C
0.08 C
(A3)
C
16X
0.10 C
0.05
C
A B
NOTE 3
K
16X
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
A1
A3
L
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
DETAIL B
DETAIL A
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
PITCH
3.30
DIMENSIONS: MILLIMETERS
0.65
16X
0.30
16X
OUTLINE
PACKAGE
RECOMMENDED
1
3.30
DIM MIN MAX
MILLIMETERS
A 0.80 1.00
A1 0.00 0.05
b 0.18 0.30
D 3.00 BSC
D2 1.25 1.55
E 3.00 BSC
E2 1.25 1.55
e 0.50 BSC
L 0.30 0.50
A3 0.20 REF
L1 0.00 0.15
K
NOTE 4
e/2
0.20 −−
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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UBLICATION ORDERING INFORMATION
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Phone: 81−3−5817−1050
NB3L202K/D
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al
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NB3L202KMNG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 1:2 HCSL FANOUT BUFFER
Lifecycle:
New from this manufacturer.
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