NB3L202K
www.onsemi.com
6
Table 5. AC TIMING CHARACTERISTICS V
DD
= V
DD_O
= 3.3 V ±10% or 2.5 V ±5%, T
A
= −40°C to 85°C (Note 15)
Symbol Characteristics Min Typ Max Unit
F
max
Maximum Input Frequency 350 MHz
T
rise
/T
fall
Rise Time / Fall Time (Notes 13, 17 and 33) (Figure 13) 175 500 700 ps
Output Slew Rate Output Slew Rate (Notes 13 and 17) 0.5 2.0 V/ns
DT
rise
/DT
fall
Rise/Fall Time Variation (Notes 17 and 26) 125 ps
Slew Rate Matching (Notes 18, 27 and 28) 20%
V
high
Voltage High (Notes 17, and 20) (Figure 14) 660 700 850 mV
V
low
Voltage Low (Notes 17, and 21) (Figure 14) −150 0 +150 mV
Input Slew Rate (Note 29 and 32) 0.35 V/ns
V
cross
absolute Absolute Crossing Point Voltages (Notes 12, 17 and 24)
Relative Crossing Point Voltages can be calculated (Notes 16, 17
and 24) (Figure 16)
250 550 mV
Total DV
cross
Total Variation of Vcross Over All Edges (Notes 17 and 25) 140 mV
Duty Cycle (Note 18) (Figure 15) 45 55 %
V
ovs
Maximum Voltage (Overshoot) (Notes 17 and 22) (Figure 14) V
high
+ 0.3 V
V
uds
Maximum Voltage (Undershoot) (Notes 17 and 23) (Figure 14) V
low
− 0.3 V
V
rb
Ringback Voltage (Note 17) (Figure 14) 0.2 N/A V
T
oe_lat
OE Latency (Note 11) 4 6 12 Cycles
t
pd
Input−to−Output Delay CLK_IN, DIF_[1:0] (Note 31) 0.6 1.0 1.4 ns
t
SKEW
Output−to−Output Skew across 2 outputs DIF_[1:0] (Notes 30 and 31) 0 5.0 20 ps
t
JITTER
f
Additive RMS Phase Jitter f
carrier
= 156.25 MHz, 12 kHz − 20 MHz Inte-
grated Range
46 80 fs
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Time from deassertion until outputs are >200 mV.
12.Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK#.
13.Measured from V
OL
= 0.175 V to V
OH
= 0.525 V. Only valid for Rising Clock and Falling Clock#.
14.This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing
15.Test configuration is R
S
= 33.2 W, R
P
= 49.9, C
L
= 2 pF, R
REF
= 475 W.
16.Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (V
high avg
− 0.700). Vcross(rel) Max = 0.550 − 0.5
(0.700 – V
high avg
), (see Figure 16 for further clarification).
17.Measurement taken from Single Ended waveform.
18.Measurement taken from differential waveform.
19.Unless otherwise noted, all specifications in this table apply to all frequencies.
20.V
high
is defined as the statistical average High value as obtained by using the Oscilloscope V
high
Math function.
21.V
low
is defined as the statistical average Low value as obtained by using the Oscilloscope V
low
Math function.
22.Overshoot is defined as the absolute value of the maximum voltage.
23.Undershoot is defined as the absolute value of the minimum voltage.
24.The crossing point must meet the absolute and relative crossing point specifications simultaneously.
25.DVcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK#. This is the maximum allowed vari-
ance in Vcross for any particular system.
26.Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
27.Matching applies to rising edge rate for clock and falling edge rate for Clock#. It is measured using a ±75 mV window centered on the average
crosspoint where clock rising meets Clock# falling. The median crosspoint is used to calculate the voltage threshold the oscilloscope is to
use for the edge rate calculations.
28.Slew Rate matching is derived using the following, 2 * (T
rise
– T
fall
) / (T
rise
+ T
fall
).
29.Input slew rate is based on single ended measurement. This is the minimum input slew rate at which the NB3L202K devices are guaranteed
to meet all performance specifications.
30.Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
31.Measured from differential cross−point to differential cross−point with scope averaging on to find mean value.
32.The differential input clock is expected to be sourced from a high performance clock oscillator.
33.Measured at 3.3 V ± 10% with typical HCSL input levels.
