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X9119TV14Z-2.7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
X9119
13
FN8162.5
July 5, 2016
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Symbol Table
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from LOW to
HIGH
Will change
from LOW to
HIGH
May change
from HIGH to
LOW
Will change
from HIGH to
LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is HIGH
Impedance
Timing Diagrams
FIGURE 8. START AND STOP TIMING
FIGURE 9. INPUT TIMING
FIGURE 10. OUTPUT TIMING
t
SU:STA
t
HD:STA
t
SU:STO
SCL
SDA
t
R
( START) (STOP)
t
F
t
R
t
F
SCL
SDA
t
HIGH
t
LOW
t
CYC
t
HD:DAT
t
SU:DAT
t
BUF
SCL
SDA
t
DH
t
AA
X9119
14
FN8162.5
July 5, 2016
Submit Document Feedback
FIGURE 11. XDCP TIMING (FOR ALL LOAD INSTRUCTIONS)
FIGURE 12. WRITE PROTECT AND DEVICE ADDRESS PINS TIMING
Timing Diagrams
SCL
SDA
R
W
(STOP)
LSB
t
WRL
SDA
SCL
...
...
...
WP
A0, A1, A2
T
SU:WPA
T
HD:WPA
(START) (STOP)
(ANY INSTRUCTION)
X9119
15
FN8162.5
July 5, 2016
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Applications information
Basic Configurations of Electronic Potentiometers
FIGURE 13. THREE-TERMINAL POTENTIOMETER; VARIABLE VOLTAGE
DIVIDER
FIGURE 14. TWO-TERMINAL VARIABLE RESISTOR; VARIABLE
CURRENT
V
R
RW
+V
R
I
Application Circuits
FIGURE 15. NONINVERTING AMPLIFIER FIGURE 16. VOLTAGE REGULATOR
FIGURE 17. OFFSET VOLTAGE ADJUSTMENT
FIGURE 18. COMPARATOR WITH HYSTERESIS
+
–
V
S
V
O
R
2
R
1
V
O
= (1+R
2
/R
1
)V
S
R
1
R
2
I
ADJ
V
O
(REG) = 1.25V (1+R
2
/R
1
)+I
adj
R
2
V
O
(REG)V
IN
317
+
–
V
S
V
O
R
2
R
1
100kΩ
10kΩ10kΩ
10kΩ
-12V+12V
TL072
V
UL
= {R
1
/(R
1
+R
2
)} V
O
(max)
RL
L
= {R
1
/(R
1
+R
2
)} V
O
(min)
+
–
V
S
V
O
R
2
R
1
}
}
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

X9119TV14Z-2.7

Mfr. #:
Buy X9119TV14Z-2.7
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs SINGLE DCP 100KOHM 1024 TAP 2-WIRE COM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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