MAX1046BETX+T Datasheet MAX1042BETX+, MAX1046BETX+, MAX1048BETX+ | P28-P30

MAX1040/MAX1042/MAX1046/MAX1048

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

28 ______________________________________________________________________________________

Output-Data Format

Figures 6–9 illustrate the conversion timing for the

MAX1040/MAX1042/MAX1046/MAX1048. All 10-bit con-

version results are output in 2-byte format, MSB first,

with four leading zeros and the LSB followed by 2 sub-

bits. Data appears on DOUT on the falling edges of

SCLK. Data is binary for unipolar mode and two’s com-

plement for bipolar mode and temperature results. See

Figures 3, 4, and 5 for input/output and temperature-

transfer functions.

ADC Transfer Functions

Figure 3 shows the unipolar transfer function for single-

ended or differential inputs. Figure 4 shows the bipolar

transfer function for differential inputs. Code transitions

occur halfway between successive-integer LSB values.

Output coding is binary, with 1 LSB = V

REF1

/ 1024 for

unipolar and bipolar operation, and 1 LSB = +0.125°C

for temperature measurements. Bipolar true-differential

results and temperature-sensor results are available in

two’s complement format, while all others are in binary.

See Tables 6, 7, and 8 for details on which setting

(unipolar or bipolar) takes precedence.

In unipolar mode, AIN+ can exceed AIN- by up to

REF1

. In bipolar mode, either input can exceed the

other by up to V

REF1

/2.

Table 18. DAC Power-Up and Power-Down Commands

CONTROL

BITS

DATA BITS

C3 C2 C1 C0 X X X X

DAC3

DAC2

DAC1

DAC0

D3 D2 D1 D0

DESCRIPTION FUNCTION

1 1 1 1 X X X X ———— 0 0 1 X Power-Up

Power up individual DAC buffers indicated by data

in DAC0 through DAC3. A one indicates the DAC

output is connected and active. A zero does not

affect the DAC’s present state.

1 1 1 1 X X X X ———— 0 1 0 X Power-Down 1

Power down individual DAC buffers indicated by

data in DAC0 through DAC3. A one indicates the

DAC output is disconnected and high impedance.

A zero does not affect the DAC’s present state.

1 1 1 1 X X X X ———— 1 0 0 X Power-Down 2

Power down individual DAC buffers indicated by

data in DAC0 through DAC3. A one indicates the

DAC output is disconnected and pulled to AGND

with a 1k

resistor. A zero does not affect the DAC’s

present state.

1 1 1 1 X X X X ———— 0 0 0 X Power-Down 3

Power down individual DAC buffers indicated by

data in DAC0 through DAC3. A one indicates the

DAC output is disconnected and pulled to AGND

with a 100k

resistor. A zero does not affect the

DAC’s present state.

1 1 1 1 X X X X ———— 1 1 1 X Power-Down 4

Power down individual DAC buffers indicated by

data in DAC0 through DAC3. A one indicates the

DAC output is disconnected and pulled to REF1 with

a 100k

resistor. A zero does not affect the DAC’s

present state.

MAX1040/MAX1042/MAX1046/MAX1048

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 29

Partial Reads and Partial Writes

If the first byte of an entry in the FIFO is partially read

(CS is pulled high after fewer than eight SCLK cycles),

the remaining bits are lost for that byte. The next byte of

data that is read out contains the next 8 bits. If the first

byte of an entry in the FIFO is read out fully, but the

second byte is read out partially, the rest of that byte is

lost. The remaining data in the FIFO is unaffected and

can be read out normally after taking CS low again, as

long as the 4 leading bits (normally zeros) are ignored.

If CS is pulled low before EOC goes low, a conversion

may not be completed and the FIFO data may not be

correct. Incorrect writes (pulling CS high before com-

pleting eight SCLK cycles) are ignored and the register

remains unchanged.

Applications Information

Internally Timed Acquisitions and

Conversions Using

CNVST

ADC Conversions in Clock Mode 00

In clock mode 00, the wake-up, acquisition, conversion,

and shutdown sequence is initiated through CNVST

and performed automatically using the internal oscilla-

tor. Results are added to the internal FIFO to be read

out later. See Figure 6 for clock mode 00 timing after a

command byte is issued. See Table 5 for details on

programming the clock mode in the setup register.

Initiate a scan by setting CNVST low for at least 40ns

before pulling it high again. The MAX1040/MAX1042/

MAX1046/MAX1048 then wake up, scan all requested

channels, store the results in the FIFO, and shut down.

After the scan is complete, EOC is pulled low and the

results are available in the FIFO. Wait until EOC goes

low before pulling CS low to communicate with the seri-

al interface. EOC stays low until CS or CNVST is pulled

low again. A temperature-conversion result, if request-

ed, precedes all other FIFO results. Temperature

results are available in 12-bit format.

FULL-SCALE

TRANSITION

111....111

INPUT VOLTAGE (LSB)

FS = V

REF

111....110

111....101

OFFSET BINARY OUTPUT CODE (LSB)

000....011

000....010

000....001

000....000

213 FS

1 LSB = V

REF

/ 1024

FS - 3/2 LSB

Figure 3. Unipolar Transfer Function—Full Scale (FS) = V

REF

OUTPUT CODE

011....111

TEMPERATURE (°C)

011....110

000....001

111....101

100....001

100....000

111....111

111....110

000....000

000....010

-256 +255.5

Figure 5. Temperature Transfer Function

011....111

-FS

INPUT VOLTAGE (LSB)

FS = V

REF

/ 2 + V

COM

REF

= V

REF+

- V

REF-

-FS = -V

REF

/ 2

011....110

011....101

000....001

000....000

111....111

OFFSET BINARY OUTPUT CODE (LSB)

100....011

100....010

100....001

100....000

(COM)

-1 +1

+FS - 1 LSB

1 LSB = V

REF

/ 1024

ZS = COM

REF

(COM)

REF

Figure 4. Bipolar Transfer Function—Full Scale (

FS) =

REF

/ 2

MAX1040/MAX1042/MAX1046/MAX1048

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

30 ______________________________________________________________________________________

Do not issue a second CNVST signal before EOC goes

low; otherwise, the FIFO can be corrupted. Wait until all

conversions are complete before reading the FIFO. SPI

communications to the DAC and GPIO registers are per-

mitted during conversion. However, coupled noise may

result in degraded ADC signal-to-noise ratio (SNR).

Externally Timed Acquisitions and

Internally Timed Conversions with

CNVST

ADC Conversions in Clock Mode 01

In clock mode 01, conversions are requested one at a

time using CNVST and performed automatically using

the internal oscillator. See Figure 7 for clock mode 01

timing after a command byte is issued.

Setting CNVST low begins an acquisition, wakes up the

ADC, and places it in track mode. Hold CNVST low for

at least 1.4µs to complete the acquisition. If reference

mode 00 or 10 is selected, an additional 45µs is

required for the internal reference to power up. If a tem-

perature measurement is being requested, reference

power-up and temperature measurement is internally

timed. In this case, hold CNVST low for at least 40ns.

Set CNVST high to begin a conversion. Sampling is

completed approximately 500ns after CNVST goes

high. After the conversion is complete, the ADC shuts

down and pulls EOC low. EOC stays low until CS or

CNVST is pulled low again. Wait until EOC goes low

before pulling CS or CNVST low. The number of CNVST

signals must equal the number of conversions request-

ed by the scan and averaging registers to correctly

update the FIFO. Wait until all conversions are com-

plete before reading the FIFO. SPI communications to

the DAC and GPIO registers are permitted during con-

(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)

DOUT

MSB1

RDS

LSB1 MSB2

SCLK

CNVST

EOC

Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion.

(CONVERSION 2)

CSW

DOV

(ACQUISITION 2)

(ACQUISITION 1)

(CONVERSION 1)

DOUT

MSB1

LSB1 MSB2

SCLK

CNVST

EOC

Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting CNVST low for each conversion.

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MAX1046BETX+T

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Manufacturer:

Maxim Integrated

Description:

Data Acquisition ADCs/DACs - Specialized 10Bit AD/DACs w/FIFO Temp Sns & GPIO Port

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