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MAX1046BETX+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
MAX1040/MAX1042/MAX1046/MAX1048
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 31
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
MSB1
t
DOV
LSB1
MSB2
(CONVERSION BYTE)
CS
DOUT
SCLK
DIN
EOC
Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required).
version. However, coupled noise may result in degrad-
ed ADC SNR.
If averaging is turned on, multiple CNVST pulses need to
be performed before a result is written to the FIFO. Once
the proper number of conversions has been performed
to generate an averaged FIFO result (as specified to the
averaging register), the scan logic automatically switch-
es the analog input multiplexer to the next requested
channel. If a temperature measurement is programmed,
it is performed after the first rising edge of CNVST follow-
ing the command byte written to the conversion register.
The temperature-conversion result is available on DOUT
once EOC has been pulled low. Temperature results are
available in 12-bit format.
Internally Timed Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequence is initiated by writing a com-
mand byte to the conversion register, and is performed
automatically using the internal oscillator. This is the
default clock mode upon power-up. See Figure 8 for
clock mode 10 timing.
Initiate a scan by writing a command byte to the conver-
sion register. The MAX1040/MAX1042/MAX1046/
MAX1048 then power up, scan all requested channels,
store the results in the FIFO, and shut down. After the
scan is complete, EOC is pulled low and the results are
available in the FIFO. If a temperature measurement is
requested, the temperature result precedes all other
FIFO results. Temperature results are available in 12-bit
format. EOC stays low until CS is pulled low again. Wait
until all conversions are complete before reading the
FIFO. SPI communications to the DAC and GPIO regis-
ters are permitted during conversion. However, coupled
noise may result in degraded ADC SNR.
MAX1040/MAX1042/MAX1046/MAX1048
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
32 ______________________________________________________________________________________
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing a command byte to the conversion
register and are performed one at a time using SCLK
as the conversion clock. Scanning, averaging and the
FIFO are disabled, and the conversion result is avail-
able at DOUT during the conversion. Output data is
updated on the rising edge of SCLK in clock mode 11.
See Figure 9 for clock mode 11 timing.
Initiate a conversion by writing a command byte to the
conversion register followed by 16 SCLK cycles. If CS
is pulsed high between the eighth and ninth cycles, the
pulse width must be less than 100µs. To continuously
convert at 16 cycles per conversion, alternate 1 byte of
zeros (NOP byte) between each conversion byte. If 2
NOP bytes follow a conversion byte, the analog cells
power down at the end of the second NOP. Set the
FBGON bit to one in the reset register to keep the inter-
nal bias block powered.
If reference mode 00 is requested, or if an external refer-
ence is selected but a temperature measurement is being
requested, wait 45µs with CS high after writing the con-
version byte to extend the acquisition and allow the inter-
nal reference to power up. To perform a temperature
measurement, write 24 bytes (192 cycles) of zeros after
the conversion byte. The temperature result appears on
DOUT during the last 2 bytes of the 192 cycles.
Temperature results are available in 12-bit format.
Conversion-Time Calculations
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external refer-
ence is in use. Use the following formula to calculate
the total conversion time for an internally timed conver-
sion in clock mode 00 and 10 (see the
Electrical
Characteristics
, as applicable):
Total conversion time =
t
CNV
x n
AVG
x n
SCAN
+ t
TS
+ t
INT-REF,SU
where:
t
CNV
= t
DOV
(where t
DOV
is dependent on clock mode
and reference mode selected)
n
AVG
= samples per result (amount of averaging)
n
SCAN
= number of times each channel is scanned; set
to one unless [SCAN1, SCAN0] = 10
t
TS
= time required for temperature measurement
(53.1µs); set to zero if temperature measurement is not
requested
t
INT-REF,SU
= t
WU
(external-reference wake-up); if a
conversion using the external reference is requested
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high. Conversion time in
externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
SCLK
DOUT
X = DON'T CARE.
MSB1 LSB1 MSB2
(ACQUISITION1)
(ACQUISITION2)
(CONVERSION1)
DIN
(CONVERSION BYTE)
CS
EOC
Figure 9. Clock Mode 11—Externally Timed Acquisition, Sampling, and Conversion without CNVST
MAX1040/MAX1042/MAX1046/MAX1048
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 33
t
CSH
SCLK
DIN
DOUT
CS
1234
32
16
8
D15
D14
D13 D12 D11
5
D15
D7
D14
D6
D13
D5
D12
D4
D0
D1
D0
t
DOD
t
DOT
t
CSS
t
CSPWH
D1
t
DOE
t
DS
t
DH
t
CH
t
CL
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
DAC/GPIO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DAC-
register update. For a software-command DAC-register
update, t
S
is valid from the rising edge of CS, which fol-
lows the last data bit in the software command word.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

MAX1046BETX+T

Mfr. #:
Buy MAX1046BETX+T
Manufacturer:
Maxim Integrated
Description:
Data Acquisition ADCs/DACs - Specialized 10Bit AD/DACs w/FIFO Temp Sns & GPIO Port
Lifecycle:
New from this manufacturer.
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