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71321LA20JG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
10
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)
(1,5)
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)
(1,5,8)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test
Load (Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
WP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required t
DW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t
WP.
ADDRESS
OE
CE
R/W
DATA
OUT
DATA
IN
(4)
(4)
2691drw 08
t
WC
t
AS
(6)
t
WR
(3)
t
OW
t
DW
t
DH
t
AW
t
WP
(2)
t
HZ
(7)
t
WZ
(7)
t
HZ
(7)
t
WC
ADDRESS
CE
R/W
DATA
IN
t
AS
(6)
t
EW
(2)
t
WR
t
DW
t
DH
t
AW
2691 drw 09
(3)
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
11
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(6)
NOTES:
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (SA or LA)..
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
Symbol Parameter Min.Max.Min.Max.Unit
BUSY TIMING (For MASTER 71321)
t
BAA
BUSY Access Time from Address
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address
____
20
____
20 ns
t
BA C
BUSY Access Time from Chip Enable
____
20
____
20 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
20 ns
t
WH
Write Hold After BUSY
(5)
12
____
15
____
ns
t
WDD
Write Pulse to Data Delay
(1 )
____
50
____
50 ns
t
DD D
Write Data Valid to Read Data Delay
(1)
____
35
____
35 ns
t
AP S
Arbitration Priority Set-up Time
(2 )
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3 )
____
25
____
35 ns
BUSY INPUT TIMING (For SLAVE 71421)
t
WB
Write to BUSY Input
(4 )
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
12
____
15
____
ns
t
WDD
Write Pulse to Data Delay
(1 )
____
40
____
50 ns
t
DD D
Write Data Valid to Read Data Delay
(1)
____
30
____
35 ns
2691 tbl 10a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol Parameter Min.Max.Min.Max.Unit
BUSY TIMING (For MASTER 71321)
t
BAA
BUSY Access Time from Address
____
20
____
30 ns
t
BDA
BUSY Disable Time from Address
____
20
____
30 ns
t
BA C
BUSY Access Time from Chip Enable
____
20
____
30 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
30 ns
t
WH
Write Hold After BUSY
(5)
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1 )
____
60
____
80 ns
t
DD D
Write Data Valid to Read Data Delay
(1)
____
35
____
55 ns
t
AP S
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3 )
____
35
____
50 ns
BUSY INPUT TIMING (For SLAVE 71421)
t
WB
Write to BUSY Input
(4 )
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1 )
____
60
____
80 ns
t
DD D
Write Data Valid to Read Data Delay
(1)
____
35
____
55 ns
2691 tbl 10b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
12
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
"B"
ATA
OUT"B"
DATA
IN "A"
ADDR
"A"
MATCH
VALID
MATCH
VALID
R/W
"A"
BUSY
"B"
t
APS
(1)
2691 drw 10
t
BAA
Timing Waveform of Write with Port-to-Port Read and BUSY
(2,3,4)
NOTES:
1. To ensure that the earlier of the two ports wins.
tAPS is ignored for Slave (IDT71421).
2. CE
L = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
NOTES:
1. t
WH must be met for both BUSY input (IDT71421, slave) or output (IDT71321, Master).
2. BUSY is asserted on port "B" blocking R/W
"B", until BUSY"B" goes HIGH.
3. t
WB is only for the slave version (IDT71421).
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY
(4)
BUSY
"B"
2691 drw 11
R/W
"A"
t
WP
t
WH
t
WB
R/W
"B"
(2)
(1)
(3)
,
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

71321LA20JG

Mfr. #:
Buy 71321LA20JG
Manufacturer:
IDT
Description:
SRAM 2KX8 DUAL PORT MSTR W/INT
Lifecycle:
New from this manufacturer.
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