6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
13
Timing Waveform of BUSY Arbitration Controlled by CE Timing
(1)
Timing Waveform of BUSY Arbritration Controlled
by Address Match Timing
(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t
APS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (IDT71321 only).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(1)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
tAPS
(2)
ADDR "A"
AND "B"
ADDRESSES MATCH
tBAC tBDC
CE"B"
CE"A"
BUSY"A"
2691 drw 12
BUSY
"B"
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
t
APS
(2)
ADDR
"A"
ADDR
"B"
2691 drw 13
t
BAA
t
BDA
t
RC
or t
WC
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
Symbol Parameter Min. Max. Min. Max. Unit
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
INS
Interrupt Set Time
____
20
____
25 ns
t
INR
Interrupt Reset Time
____
20
____
25 ns
2691 tbl 11a
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
14
Timing Waveform of Interrupt Mode
(1)
SET INT
CLEAR INT
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range
(1)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
tINS
ADDR"A"
INT"B"
INTERRUPT ADDRESS
t
WC
tAS
R/W"A"
tWR
2691 drw 14
(3)
(3)
(2)
(4)
t
RC
INTERRUPT CLEAR ADDRESS
A
DDR
"B"
OE
"B"
t
INR
INT
"B"
2691 drw 15
t
AS
(3)
(3)
(2)
,
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol Parameter Min. Max. Min. Max. Unit
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
INS
Interrupt Set Time
____
25
____
45 ns
t
INR
Interrupt Reset Time
____
25
____
45 ns
2691 tbl 11b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
15
Truth Table III — Address BUSY Arbitration
Truth Table I. Non-Contention Read/Write Control
(4)
NOTES:
1. Pins BUSY
L and BUSYR are both outputs for IDT71321 (Master). Both are inputs for IDT71421 (Slave). BUSYX outputs on the IDT71321 are open drain, not push-
pull outputs. On slaves the BUSY
X input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t
APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSY
L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSY
R outputs are driving LOW regardless of actual logic level on the pin.
Truth Tables
Truth Table II. Interrupt Flag
(1,4)
NOTES:
1. A
0L – A10L A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t
WDD and tDDD timing.
4. 'H' = V
IH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
NOTES:
1. Assumes BUSY
L = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSY
R = VIL, then No Change.
4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE
Left or Right Port
(1)
FunctionR/W
CE OE
D
0-7
X H X Z Port Disabled and in Power-Down Mode, ISB
2
or ISB
4
XHX Z
CE
R
= CE
L
= V
IH
, Power-Down Mode, ISB
1
or ISB
3
LLXDATA
IN
Data on Port Written Into Memory
(2 )
HLLDATA
OUT
Data in Memory Output on Por
t
(3 )
H L H Z High Impedance Outputs
2691 tbl 12
Left Port Right Port
FunctionR/W
L
CE
L
OE
L
A
10L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
10R
-A
0R
INT
R
LLX7FFXXXX X L
(2 )
Set Right INT
R
Flag
XXXXXXLL7FF H
(3)
Reset Right INT
R
Flag
XXX X L
(3 )
L L X 7FE X Set Left INT
L
Flag
XLL7FE H
(2 )
X X X X X Reset Left INT
L
Flag
2691 tbl 13
Inputs Outputs
Function
CE
L
CE
R
A
0L
-A
10L
A
0R
-A
10R
BUSY
L
(1 )
BUSY
R
(1)
XXNO MATCH H H Normal
HX MATCH H H Normal
XH MATCH H H Normal
L L MATCH (2) (2) Write Inhibit
(3 )
2691 tbl 14

71321LA20JG

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 2KX8 DUAL PORT MSTR W/INT
Lifecycle:
New from this manufacturer.
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