OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

71321LA20JG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
7
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. 'X' in part numbers indicates power rating (SA or LA).
3. This parameter is guaranteed by device characterization, but is not production tested.
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range
(2)
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
UnitSymbol Parameter Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 20
____
25
____
ns
t
AA
Address Access Time
____
20
____
25 ns
t
ACE
Chip Enable Access Time
____
20
____
25 ns
t
AOE
Output Enable Access Time
____
11
____
12 ns
t
OH
Output Hold from Address Change 3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,3)
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,3)
____
10
____
10 ns
t
PU
Chip Enable to Power Up Time
(3 )
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(3 )
____
20
____
25 ns
2691 tbl 08a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
UnitSymbol Parameter Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 35
____
55
____
ns
t
AA
Address Access Time
____
35
____
55 ns
t
ACE
Chip Enable Access Time
____
35
____
55 ns
t
AOE
Output Enable Access Time
____
20
____
25 ns
t
OH
Output Hold from Address Change 3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,3)
0
____
5
____
ns
t
HZ
Output High-Z Time
(1,3)
____
15
____
25 ns
t
PU
Chip Enable to Power Up Time
(3 )
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(3 )
____
35
____
50 ns
2691 tbl 08b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
8
Timing Waveform of Read Cycle No. 2, Either Side
(3)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = V
IH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last t
AOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 1, Either Side
(1)
NOTES:
1. R/W = V
IH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. t
BDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last t
AOE, tACE, tAA, and tBDD.
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
2691 drw 06
t
BDDH
(2,3)
BUSY
OUT
CE
t
ACE
t
AOE
t
HZ
t
LZ
t
PD
VALID DATA
t
PU
50%
OE
DATA
OUT
CURRENT
I
CC
I
SS
50%
2691 drw 07
(4)
(1)
(1)
(2)
(2)
(4)
t
LZ
t
HZ
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
9
AC Electrical Characteristics Over the
Operating Temeprature and Supply Voltage Range
(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. For Master/Slave combination, t
WC = tBAA + tWP, since R/W = VIL must occur after tBAA .
3. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required t
DW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t
WP.
4. 'X' in part numbers indicates power rating (SA or LA).
Symbol Parameter
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
UnitMin. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time
(2 )
20
____
25
____
ns
t
EW
Chip Enable to End-of-Write 15
____
20
____
ns
t
AW
Address Valid to End-of-Write 15
____
20
____
ns
t
AS
Address Set-up Time 0
____
0
____
ns
t
WP
Write Pulse Width
(3 )
15
____
15
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
DW
Data Valid to End-of-Write 10
____
12
____
ns
t
HZ
Output High-Z Time
(1)
____
10
____
10 ns
t
DH
Data Hold Time 0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1)
____
10
____
10 ns
t
OW
Output Active from End-of-Write
(1 )
0
____
0
____
ns
2691 tbl 09a
Symbol Parameter
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
UnitMin. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time
(2 )
35
____
55
____
ns
t
EW
Chip Enable to End-of-Write 30
____
40
____
ns
t
AW
Address Valid to End-of-Write 30
____
40
____
ns
t
AS
Address Set-up Time 0
____
0
____
ns
t
WP
Write Pulse Width
(3 )
25
____
30
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
DW
Data Valid to End-of-Write 15
____
20
____
ns
t
HZ
Output High-Z Time
(1)
____
15
____
25 ns
t
DH
Data Hold Time 0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1)
____
15
____
30 ns
t
OW
Output Active from End-of-Write
(1 )
0
____
0
____
ns
2691 tbl 09b
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

71321LA20JG

Mfr. #:
Buy 71321LA20JG
Manufacturer:
IDT
Description:
SRAM 2KX8 DUAL PORT MSTR W/INT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet