6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,4)
(VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. At f = f
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input
levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc = 5V, T
A=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE
L
and CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(2)
COM'L SA
LA
11 0
11 0
250
200
110
110
220
170
mA
IND SA
LA
____
____
____
____
110
110
270
220
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
and CE
R
= V
IH
f = f
MAX
(2)
COM'L SA
LA
30
30
65
45
30
30
65
45
mA
IND SA
LA
____
____
____
____
30
30
75
55
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5 )
Active Port Outputs Disabled,
f=f
MAX
(2 )
COM'L SA
LA
65
65
165
125
65
65
150
115
mA
IND SA
LA
____
____
____
____
65
65
170
140
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(3)
COM'L SA
LA
1.0
0.2
15
5
1.0
0.2
15
5
mA
IND SA
LA
____
____
____
____
1.0
0.2
30
10
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5 )
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(2)
COM'L SA
LA
60
60
155
11 5
60
60
145
105
mA
IND SA
LA
____
____
____
____
60
60
165
130
2691 tbl 04a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE
L
and CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(2 )
COM'L SA
LA
80
80
165
120
65
65
155
110
mA
IND SA
LA
____
____
____
____
65
65
190
140
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
and CE
R
= V
IH
f = f
MAX
(2 )
COM'L SA
LA
25
25
65
45
20
20
65
35
mA
IND SA
LA
____
____
____
____
20
20
70
50
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(2 )
COM'L SA
LA
50
50
125
90
40
40
110
75
mA
IND SA
LA
____
____
____
____
40
40
125
90
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(3 )
COM'L SA
LA
1.0
0.2
15
4
1.0
0.2
15
4
mA
IND SA
LA
____
____
____
____
1.0
0.2
30
10
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(2 )
COM'L SA
LA
45
45
11 0
85
40
40
100
70
mA
IND SA
LA
____
____
____
____
40
40
110
85
2691 tbl 04b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (V
CC = 5.0V ± 10%)
NOTE:
1. At Vcc
< 2.0V leakages are undefined.
Data Retention Characteristics (LA Version Only)
NOTES:
1. V
CC = 2V, TA = +25°C, and is not production tested.
2. t
RC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
Data Retention Waveform
V
CC
CE
4.5V 4.5V
DATA RETENTION MODE
t
CDR
t
R
V
IH
V
IH
V
DR
V
DR
2.0V
2691 drw 04
,
Symbol Parameter Test Conditions
71321SA
71421SA
71321LA
71421LA
UnitMin. Max. Min. Max.
|I
LI
| Input Leakage Current
(1 )
V
CC
= 5.5V, V
IN
= 0V to V
CC
___
10
___
A
|I
LO
|
Output Leakage Current
(1 )
CE = V
IH
, V
OUT
= 0V to V
CC
,
V
CC
- 5.5V
___
10
___
A
V
OL
Output Low Voltage (I/O
0
-I/O
7
)I
OL
= 4mA
___
0.4
___
0.4 V
V
OL
Open Drain Output
Low Voltage (BUSY/INT)
I
OL
= 16mA
___
0.5
___
0.5 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
2.4
___
V
2691 tbl 05
Symbol Parameter Test Condition Min. Typ.
(1 )
Max. Unit
V
DR
V
CC
for Data Retention 2.0
____
0V
I
CCDR
Data Retention Current
V
CC
= 2.0V, CE > V
CC
- 0.2V COM'L
____
100 1500
µA
V
IN
> V
CC
- 0.2V or VI
N
< 0.2V IND
____
100 4000
µA
t
CD R
(3 )
Chip Deselect to Data Retention Time 0
____ ____
ns
t
R
(3 )
Operation Recovery Time t
RC
(2)
____ ____
ns
2691 tbl 06
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
6
5V
1250
30pF*
775
DATA
OUT
5V
1250
775
5pF*
DATA
OUT
2691 drw 05
5V
270
30pF*
BUSY or INT
*100pF for 55ns versions
*100pF for 55ns versions
,
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for t
HZ, tLZ, tWZ, and tOW)
* Including scope and jig.
Figure 3. BUSY and INT
AC Output Test Load
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1,2 and 3
2691 tbl 07

71321LA20JG

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 2KX8 DUAL PORT MSTR W/INT
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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