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VNQ5050K-E

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
Electrical specifications VNQ5050K-E
10/31 Doc ID 10864 Rev 7
Note: To ensure long term reliability under heavy overload or short circuit conditions, protection
and related diagnostic signals must be used together with a proper software strategy. If the
device is subjected to abnormal conditions, this software must limit the duration and number
of activation cycles
Table 8. Status pin (V
SD
=0)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
STAT
Status low output
voltage
I
STAT
= 1.6 mA, V
SD
=0V 0.5 V
I
LSTAT
Status leakage current
Normal operation or V
SD
=5V,
V
STAT
= 5V
10 μA
C
STAT
Status pin input
capacitance
Normal operation or V
SD
=5V,
V
STAT
= 5V
100 pF
V
SCL
Status clamp voltage
I
STAT
= 1mA
I
STAT
= - 1mA
5.5
-0.7
7V
V
Table 9. Protections
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
limH
DC short circuit
current
V
CC
=13V
5V<V
CC
<36V
13.5 19 26.5
26.5
A
A
I
limL
Short circuit current
during thermal cycling
V
CC
=13V
T
R
<T
j
<T
TSD
7A
T
TSD
Shutdown
temperature
150 175 200 °C
T
R
Reset temperature
T
RS
+ 1
T
RS
+ 5
°C
T
RS
Thermal reset of
STATUS
135 °C
T
HYST
Thermal hysteresis
(T
TSD
-T
R
)
7°C
t
SDL
Status delay in
overload conditions
T
j
>T
TSD
(See Figure 4)20μs
V
DEMAG
Turn-off output voltage
clamp
I
OUT
=2A; V
IN
=0; L=6mH
V
CC
-41
V
CC
-46
V
CC
-52
V
V
ON
Output voltage drop
limitation
I
OUT
=0.1A (see Figure 5)
T
j
= -40°C...+150°C
25 mV
Table 10. Open-load detection
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
OL
Open-load on-state
detection threshold
V
IN
= 5V, 8V<Vcc<18V
(See Figure 22.)
10 70 mA
t
DOL(on)
Open-load on-state
detection delay
I
OUT
= 0A, V
CC
=13V
(See Figure 4.)
200 μs
VNQ5050K-E Electrical specifications
Doc ID 10864 Rev 7 11/31
t
POL
Delay between input
falling edge and status
rising edge in open-
load condition
I
OUT
= 0A (See Figure 4.) 200 500 1000 μs
V
OL
Open-load off-state
voltage detection
threshold
V
IN
= 0V, 8V<V
CC
<16V
(See Figure 23.)
24V
t
DSTKON
Output short circuit to
V
cc
detection delay at
turn-off
(See Figure 4.)180t
POL
μs
Table 11. Logic input
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
Input low level 0.9 V
I
IL
Low level input current V
IN
= 0.9V 1 μA
V
IH
Input high level 2.1 V
I
IH
High level input current V
IN
= 2.1V 10 μA
V
I(hyst)
Input hysteresis
voltage
0.25 V
V
ICL
Input clamp voltage
I
IN
= 1mA
I
IN
= -1mA
5.5
-0.7
7V
V
V
SDL
STAT_DIS low level
voltage
0.9 V
I
SDL
Low level STAT_DIS
current
V
SD
=0.9V 1 μA
V
SDH
STAT_DIS high level
voltage
2.1 V
I
SDH
High level STAT_DIS
current
V
SD
=2.1V 10 μA
V
SD(hyst)
STAT_DIS hysteresis
voltage
0.25 V
V
SDCL
STAT_DIS clamp
voltage
I
SD
=1mA
I
SD
=-1mA
5.5
-0.7
7V
V
Table 10. Open-load detection (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Electrical specifications VNQ5050K-E
12/31 Doc ID 10864 Rev 7
Figure 4. Status timings
Figure 5. Output voltage drop limitation
Table 12. Truth table
Conditions Input Output Status (V
SD
=0V)
(1)
Normal operation
L
H
L
H
H
H
Current limitation
L
H
L
X
H
H
V
IN
V
STAT
t
POL
OPEN LOAD STATUS TIMING (without external pull-up)
I
OUT
< I
OL
V
OUT
< V
OL
t
DOL(on)
V
IN
V
STAT
OPEN LOAD STATUS TIMING (with external pull-up)
I
OUT
< I
OL
V
OUT
> V
OL
t
DOL(on)
V
IN
V
STAT
OVER TEMP STATUS TIMING
t
SDL
t
SDL
T
j
> T
TSD
V
IN
V
STAT
t
DSTKON
OUTPUT STUCK TO Vcc
I
OUT
> I
OL
V
OUT
> V
OL
t
DOL(on)
V
on
I
out
V
cc
-V
out
T
j
=150
o
C
T
j
=25
o
C
T
j
=-40
o
C
V
on
/R
on(T)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

VNQ5050K-E

Mfr. #:
Buy VNQ5050K-E
Manufacturer:
STMicroelectronics
Description:
Gate Drivers Quad Ch HiSide Drivr
Lifecycle:
New from this manufacturer.
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