VNQ5050K-E Electrical specifications
Doc ID 10864 Rev 7 13/31
Figure 6. Switching characteristics
Over temperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Output voltage > V
OL
L
H
H
H
L
(2)
H
Output current < I
OL
L
H
L
H
H
(3)
L
1. If the V
SD
is high, the STATUS pin is in a high impedance.
2. The STATUS pin is low with a delay equal to t
DSTKON
after INPUT falling edge.
3. The STATUS pin becomes high with a delay equal to t
POL
after INPUT falling edge.
Table 13. Electrical transient requirements (part 1/3)
ISO 7637-2:
2004(E)
test Pulse
Test levels
(1)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
III IV
1 -75 V -100 V
5000
pulses
0.5 s 5 s 2 ms, 10 Ω
2a +37 V +50 V
5000
pulses
0.2 s 5 s 50 μs, 2 Ω
3a -100 V -150 V 1h 90 ms 100 ms 0.1 μs, 50 Ω
3b +75 V +100 V 1h 90 ms 100 ms 0.1 μs, 50 Ω
Table 12. Truth table (continued)
Conditions Input Output Status (V
SD
=0V)
(1)
V
OUT
dV
OUT
/dt
(on)
t
r
80%
10%
t
f
dV
OUT
/dt
(off)
t
d(off)
t
d(on)
INPUT
t
t
90%
t
Won
t
Woff
