NCP5395
http://onsemi.com
13
ELECTRICAL CHARACTERISTICS
0°C < T
A
< 70°C; 0°C < T
J
< 125°C; 4.75 < V
CC
< 5.25 V; All DAC Codes; C
VCC
= 0.1 mF unless otherwise noted.
Parameter UnitMaxTypMinTest Conditions
VID INPUTS
Threshold 450 600 770 mV
VR11 Mode Leakage −100 − 100 nA
AMD Mode Input Bias Current 10 − 25
mA
Delay before Latching VID Change
(VID Deskewing)
Measured from the edge of the 1
st
VID change
200 − 300 ns
Delay Before Responding to Invalid or Shutdown
Codes (Remove Spec)
Note: DAC must hold the last valid
VID during this period
− − −
ms
DIGITAL DAC SLEW RATE LIMITER
Slew Rate Limit (Intel Mode) 12.5 − 15
mV/ms
Slew Rate Limit (AMD Mode) 3.125 − 3.75
mV/ms
Soft−Start Slew Rate − 0.84 −
mV/ms
INPUT SUPPLY CURRENT
V
CC
Operating Current EN Low, No PWM 20 − 40 mA
PHASE SHEDDING
CS referred ph shed bias CS2 through CS4 − 66 − mV
V
CCP
SUPPLY VOLTAGE
V
CCP
UVLO Start Threshold 8.2 9.0 9.5 V
V
CCP
UVLO Stop Threshold 7.2 8.0 8.5 V
V
CCP
UVLO Hysteresis − 1.0 − V
V
CCP
POR Voltage at which the Driver OVP
becomes active
TBD 3.2 TBD
BOOST PIN UVLO
BOOST V
CC
UVLO Start Threshold 3.5 4.0 V
BOOST V
CC
UVLO Stop Threshold 3.3 3.8 V
BOOST V
CC
UVLO Hysteresis 200 mV
BOOST SUPPLY CURRENT
I
VCCP_NORM
Quiescent Supply Current in Normal
Operation
EN = V
CC
, PWM = OSC, F
SW
=
100k, C
LOAD
= 0 p, V
CCP
= 12 V
− − 42 mA
I
VCC_SBC
Standby Current EN = GND; No switching,
V
CCP
= 12 V
20 − 40 mA
I
BST1
Quiescent Supply Current in Normal Operation IN = V
CCP
, V
CCP
= 12 V − 10 TBD mA
I
BST2
Quiescent Supply Current in Normal Operation IN = GND, V
CCP
= 12 V − 10 TBD mA
I
BST3
Quiescent Supply Current in Normal Operation IN = GND, V
CCP
= 12 V − 10 TBD
I
BST1_SD
Standby Current IN = V
CCP
, V
CCP
= 12 V − 0.25 − mA
I
BST2_SD
Standby Current IN = GND, V
CCP
= 12 V − 0.25 − mA
I
BST3_SD
Standby Current IN = GND, V
CCP
= 12 V − 0.25 − mA
STARTUP HIGH SIDE SHORT TRIP (Active only during 1
st
power on)
V
swx
Output Overvoltage Trip Threshold at Startup Power Startup time, V
CC
> 9 V 1.75 − 2.0 V
3. Design guaranteed.
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
5. Guaranteed by design; not tested in production.
6. Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
7. No DAC offset is implemented for AMD operation.
