NCP5395
http://onsemi.com
26
PWM Comparators
Four PWM comparators are incorporated within the IC.
The non−inverting input of the comparators is connected to
the output of the error amplifier. The inverting input is
connected to a summed output of the phase current and the
oscillator ramp voltage with an offset. The output of the
comparator generates the PWM control signals.
During steady state operation, the duty cycle will center
on the valley of the saw−tooth waveform. During a transient
event, the controller will operate somewhat hysteretic, with
the duty cycle climbing along either the down ramp, up
ramp, or both.
Soft−Start
Soft−start is implemented internally. A digital counter
steps the DAC up from zero to the target voltage based on the
predetermined rate in the spec table. There are 2 possible
soft start modes: VR11 and AMD. AMD mode simply ramps
V
core
from 0 V directly to the DAC setting. The VR11 mode
ramps DAC to 1.1 V, pauses for 500 ms, reads the DAC
setting, then ramps to the final DAC setting.
Digital Slew Rate Limiter / Soft Start Block
The slew rate limiter and the soft−start block are to be
implemented with a digital up/down counter controlled by
an oscillator that is synchronized to VID line changes.
During soft start the DAC will ramp at the soft−start rate,
after soft start is complete the ramp rate will follow either the
Intel or the AMD slew rate depending on the mode.
Under Voltage Lockouts
An under voltage circuit senses the V
CC
input of the
controller and the V
CCP
input of the driver. During power up
the input voltage to the controller is monitored. The PWM
outputs and the soft start circuit are disabled until the input
voltage exceeds the threshold voltage of the comparators.
Hysteresis is incorporated within the comparators.
The DRVON is held low until V
CCP
reaches the start
threshold during startup. If V
CCP
decreases below the stop
threshold, the output gate will be forced low unit input
voltage V
CCP
rises above the startup threshold.
Over Current Latch
A programmable over current latch is incorporated within
the IC. The oscillator pin provides the reference voltage for
this pin. A resistor divider from the OSC pin generates the
ILIM voltage. The latch is set when the current information
on V
droop
exceeds the programmed voltage plus a 1.3 V
offset. DRVON is immediately set low. To recover the part
must be reset by the EN pin or by cycling V
CC
.
UVLO Monitor
If the output voltage falls greater than 300 mV below the
DAC voltage for more than 5 ms the UVLO comparator will
trip sending the VR_RDY signal low.
Over Voltage Protection
The output voltage is monitored at the input of the
differential amplifier. During normal operation, if the output
voltage exceeds the DAC voltage by 185 mV, or 285 mV if
in AMD mode, the VR_RDY flag will transition low the
high side gate drivers set to low, and the low side gate drivers
are all brought to high until the voltage falls below the OVP
threshold. If the over voltage trip 8 times the output voltage
will shut down. The OVP will not shut down the controller
if it occurs during soft−start. This is to allow the controller
to pull the output down to the DAC voltage and start up into
a pre−charged output.
V
CCP
Power ON Reset OVP
The V
CCP
power on reset OVP feature is used to protect
the CPU during start up. When V
CCP
is higher than 3.2 V, the
gate driver will monitor the switching node SW pin. If
SWNx pin higher than 1.9 V, the bottom gate will be forced
to high for discharge of the output capacitor. This works best
if the 5 volt standby is diode OR’ed into V
CCP
with the 12 V
rail. The fault mode will be latched and the DRVON pin will
be forced to low, unless V
CCP
is reduced below the UVLO
threshold.
Power Saving Mode
The controller is designed to allow power saving mode to
maintain a maximum efficiency. When a low PSI signal
from microcontroller is received, the controller will keep
one phase operating while shedding other phases. The active
one phase will operate in diode emulation mode, minimizing
power losses in light load. When the low PSI signal is
de−asserted, the dropped phases will be pulled back in to be
ready for heavy load.
Adaptive Non−overlap
The non−overlap dead time control is used to avoid shoot
through damage to the power MOSFETs. When the PWM
signal pull high, DRVL will go low after a propagation
delay, the controller monitors the switching node (SWN) pin
voltage and the gate voltage of the MOSFET to know the
status of the MOSFET. When the low side MOSFET status
is off an internal timer will delay turn on of the high–side
MOSFET. When the PWM pull low, gate DRVH will go low
after the propagation delay (tpdDRVH). The time to turn off
the high side MOSFET is depending on the total gate charge
of the high−side MOSFET. A timer will be triggered once
the high side MOSFET is turn off to delay the turn on the
low−side MOSFET.
Layout Guidelines
Layout is very important thing for design a DC−DC
converter. Bootstrap capacitor and V
in
capacitor are most
critical items, it should be placed as close as to the controller
IC. Another item is using a GND plane. Ground plane can
provide a good return path for gate drives for reducing the
ground noise. Therefore GND pin should be directly
connected to the ground plane and close to the low−side
MOSFET source pin. Also, the gate drive trace should be
considered. The gate drives has a high di/dt when switching,
therefore a minimized gate drives trace can reduce the di/dv,
raise and fall time for reduce the switching loss.
