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NCP5395MNR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
NCP5395
http://onsemi.com
7
ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
ELECTRICAL INFORMATION
Controller Power Supply Voltages to GND
V
CC
−0.3, 7 V
Driver Power Supply Voltages to GND V
CCP
−0.3, 15 V
High−Side Gate Driver Supplies: BSTx to SWNx V
BST
− V
SWN
35 V wrt/GND
40 V ≤ 50 ns wrt/GND
−0.3, 15 wrt/SWN
V
High−Side FET Gate Driver Voltages: TGx to SWNx V
TG
− V
SWN
BOOT + 0.3 V
35 V ≤ 50 ns wrt/GND
−0.3, 15 wrt/SWN
−2 V (200 ns)
V
Switch Node: SWNx V
SWN
35
40 V ≤ 50 ns wrt/GND
−5 VDC
−10 V (200 ns)
V
Low−Side Gate Drive: BGx V
BG
− AGND V
CC
+ 0.3 V
−0.3 VDC (200 ns)
V
Logic Inputs V
LOGIC
−0.3, 6 V
GND V
GND
0 V
V− GND ±300 mV
Imon Out V
IMON
1.1 V
All Other Pins −0.3, 5.5 V
THERMAL INFORMATION
Thermal Characteristic
QFN Package (Note 1)
R
q
JA
TBD °C/W
Operating Junction Temperature Range (Note 2) T
J
0 to 125 °C
Operating Ambient Temperature Range T
AMB
0 to +70 °C
Maximum Storage Temperature Range T
STG
−55 to +150 °C
Moisture Sensitivity Level
QFN Package
MSL 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*All signals referenced to GND unless noted otherwise.
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. Operation at −40°C to 0°C guaranteed by design, not production tested.
NCP5395
http://onsemi.com
8
ELECTRICAL CHARACTERISTICS
0°C < T
A
< 70°C; 0°C < T
J
< 125°C; 4.75 < V
CC
< 5.25 V; All DAC Codes; C
VCC
= 0.1 mF unless otherwise noted.
Parameter Test Conditions Min Typ Max Unit
ERROR AMPLIFIER
Input Bias Current −200 − 200 nA
Open Loop DC Gain C
L
= 60 pF to GND,
R
L
= 10 kW to GND
− 100 − dB
Open Loop Unity Gain Bandwidth C
L
= 60 pF to GND,
R
L
= 10 kW to GND
− 18 − MHz
Open Loop Phase Margin C
L
= 60 pF to GND,
R
L
= 10 kW to GND
− 70 − °
Slew Rate
DV
in
= 100 mV, G = −10V/V,
DV
out
= 1.5 V − 2.5 V,
C
L
= 60 pF to GND,
DC Load = ±125 mA to GND
− 10 −
V/ms
Maximum Output Voltage 10 mV of Overdrive,
I
SOURCE
= 2.0 mA
3.0 − − V
Minimum Output Voltage 10 mV of Overdrive,
I
SINK
= 500 mA
− − 75 mV
Output Source Current 10 mV of Overdrive,
V
out
= 3.5 V
1.5 2.0 − mA
Output Sink Current 10 mV of Overdrive,
V
out
= 0.1 V
0.75 1.0 − mA
DIFFERENTIAL SUMMING AMPLIFIER
V+ Input Pull down Resistance DRVON = low
DRVON = high
−
−
0.6
6.0
−
−
kW
V+ Input Bias Voltage DRVON = low
DRVON = high
−
−
0.5
0.86
−
−
V
Input Voltage Range (Note 4) −0.3 − 3.0 V
−3 dB Bandwidth C
L
= 80 pF to GND,
R
L
= 10 kW to GND
− 15 − MHz
Closed Loop DC gain VS to Diffout (Note 4) VS+ to VS− = 0.5 V to 1.6 V 0.98 1.0 1.02 V/V
Maximum Output Voltage 10 mV of Overdrive,
I
SOURCE
= 2 mA
3.0 − − V
Minimum Output Voltage 10 mV of Overdrive,
I
SINK
= 1 mA
− − 0.5 V
Output Source Current 10 mV of Overdrive,
V
out
= 3 V
1.5 2.0 − mA
Output Sink Current 10 mV of Overdrive,
V
out
= 0.2 V
1.0 1.5 − mA
INTERNAL OFFSET VOLTAGE
Offset Voltage to the (+) Pin of the Error Amp & the
VDRP Pin
−2 0 +2 mV
3. Design guaranteed.
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
5. Guaranteed by design; not tested in production.
6. Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
7. No DAC offset is implemented for AMD operation.
NCP5395
http://onsemi.com
9
ELECTRICAL CHARACTERISTICS
0°C < T
A
< 70°C; 0°C < T
J
< 125°C; 4.75 < V
CC
< 5.25 V; All DAC Codes; C
VCC
= 0.1 mF unless otherwise noted.
Parameter UnitMaxTypMinTest Conditions
VDROOP AMPLIFIER
Input Bias Current −200 − 200 nA
Inverting Voltage Range 0 1.3 3.0 V
Open Loop DC Gain C
L
= 20 pF to GND including ESD
R
L
= 1 kW to GND
− 100 − dB
Open Loop Unity Gain Bandwidth C
L
= 20 pF to GND including ESD
R
L
= 1 kW to GND
− 18 − MHz
Open Loop Phase Margin C
L
= 20 pF to GND including ESD
R
L
= 1 kW to GND
− 70 − °
Slew Rate C
L
= 20 pF to GND including ESD
R
L
= 1 kW to GND
− 10 −
V/ms
Maximum Output Voltage 10 mV of Overdrive,
I
SOURCE
= 4.0 mA
3.0 − − V
Minimum Output Voltage 10 mV of Overdrive,
I
SINK
= 1.0 mA
− − 1.0 V
Output Source Current 10 mV of Overdrive,
V
out
= 3.0 V
4.0 − − mA
Output Sink Current 10 mV of Overdrive,
V
out
= 1.0 V
1.0 − − mA
CSSUM AMPLIFIER
Current Sense Input to CSSUM Gain −75 mV < CS < 75 mV −3.793 −3.70 −3.608 V/V
Current Sense Input to V
DRP
−3 dB Bandwidth C
L
= 10 pF to GND,
R
L
= 10 kW to GND
− 12 − MHz
Current Summing Amp Output Offset Voltage CSx − CSNx = 0, CSx = 1 V −8.0 − +8.0 mV
Maximum CSSUM Output Voltage CSx − CSxN = −0.2 V
(all phases) I
SOURCE
= 1 mA
3.0 − − V
Minimum CSSUM Output Voltage CSx − CSxN = 0.7 V
(all phases) I
SINK
= 1 mA
− − 0.3 V
Output Source Current V
out
= 3.0 V 1.0 − − mA
Output Sink Current V
out
= 0.3 V 4.0 − − mA
PSI
Enable High Input Leakage Current External 1k Pull−up to 3.3 V − − 1.0
mA
Threshold 450 600 770 mV
Delay − 100 − ns
DRVON
Output High Voltage
Sourcing 500 mA
3.0 − − V
Output Low Voltage
Sinking 500 mA
− − 0.7 V
Delay Time Propagation delays − 10 − ns
Rise Time C
L
(PCB) = 20 pF,
DVo = 10% to 90%
− 10 − ns
Fall Time C
L
(PCB) = 20 pF,
DVo = 10% to 90%
− 10 − ns
Internal Pull−Down Resistance 35 70 140
kW
V
CC
Voltage when DRVON Output Valid − − 2.0 V
3. Design guaranteed.
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
5. Guaranteed by design; not tested in production.
6. Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
7. No DAC offset is implemented for AMD operation.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

NCP5395MNR2G

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Buy NCP5395MNR2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers 2/3/4 PH CTRL/DRIVE
Lifecycle:
New from this manufacturer.
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