MMA6222EG
Sensors
Freescale Semiconductor 19
SECTION 4 SERIAL COMMUNICATIONS
Digital data communication with MMA62XXEG is completed through synchronous serial transfers via the SPI port. Conventional
SPI protocol is employed, with MMA62XXEG acting as a slave device observing CPOL = 0, CPHA = 0, MSB first. A number of
data integrity features are incorporated into the transfer protocol.
4.1 SPI PROTOCOL
4.1.1 Overview
Each transfer is completed through a sequence of two operations, termed phases. During the first phase, the type of transfer and
associated control information is transmitted from the SPI master to MMA62XXEG. Data from MMA62XXEG is transmitted during
the second phase. Single-level queuing is employed as illustrated in Figure 4-1.
Figure 4-1 Transfer Phase Detail
Any activity on DIN or SCLK is ignored when CS is negated. Consequently, intermediate transfers involving other SPI devices
may occur between Phase One and Phase Two.
Figure 4-2 Single-Level Communications Queuing Detail
SCLK
D
IN
D
OUT
CS
Phase One: Type and Control
Phase Two: DataRequest Error
Request Error only reported on
first access following reset
SCLK
D
IN
D
OUT
CS
T1P1 T2P1
T1P2 T2P2
T3P1
T3P2
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20 Freescale Semiconductor
The first data transmitted by MMA62XXEG following reset is the Request Error message shown below. This occurs because
MMA62XXEG transmits during Phase Two and there is no corresponding Phase One for the first transfer.
Figure 4-3 Request Error Frame
4.1.2 Command Format
The following abbreviations are used in the following figures.
Commands are transferred from the SPI master to MMA62XXEG. Commands fall into three categories: acceleration data re-
quests, register operations and device test. Acceleration data requests are initiated when bit 13 from the master is set to a
logic ‘1’ state. Register operations and device test are when bit 13 is set to logic’0’ and are further distinguished by the states of
bits 15 and 14.
4.1.3 Acceleration Data Transfers
Acceleration data requests are initiated when bit 15 from the master is set to a logic ‘0’ state and bit 13 is set to a logic ‘1’ state.
The axis associated with the acceleration to be transferred is determined by D
IN
bit 14.
Figure 4-4 Acceleration Command Format
Bit Name Description
Bit Address
D
IN
D
OUT
A[4:0] Register address 12:8 12:8
D[9:0] 10-bit acceleration data N/A 9:0
Acc Acceleration data indicator 13 13
AXIS Axis specifier 14 14
P Parity N/A 12
S[1:0] Status N/A 11:10
0
SCLK
BIT
D
OUT
CS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00P0111000 00RE00
SCLK
BIT
D
IN
CS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AXIS
0
AccXXXXXXXXXXXXX
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Freescale Semiconductor 21
Acceleration data is returned as illustrated below. In addition to the acceleration value, the axis associated with the measurement
is indicated in bit 13, while bits 11 and 10 provide status information.
Figure 4-5 Acceleration Command Response
Figure 4-6 Acceleration Command Response, Self-Test Active
4.1.4 AXIS Bit
Bit 13 indicates the axis associated with acceleration data, as shown below.
4.1.5 Status Bits
Data bits 11 and 10 convey additional information regarding the acceleration data being transmitted. If an error condition is indi-
cated, bits D9 through D0 contain flags which further describe the nature of the error.
The combination S1 = 0, S0 = 0 is never transmitted by MMA62XXEG in response to an acceleration data command.
Table 4-1 AXIS Bit Definitions
AXIS Selected Axis
0 X
1 Y
Table 4-2 STATUS Bit Definitions
Status Bit
Definition
S1 S0
0 0 Not Applicable
0 1 Acceleration Data
1 0 Self-test Data
1 1 Error
SCLK
BIT
D
OUT
CS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 AXIS
P D4D3D2D1
D0
D6 D5
0
S1 S0 D9 D8 D7
SCLK
BIT
D
OUT
CS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 AXIS P D4D3D2D1 D0D6 D50 S1 S0 D9 D8 D7

MMA6222EG

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
Accelerometers XY 20 / 20 DIGITAL
Lifecycle:
New from this manufacturer.
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