MMA6222EG
Sensors
Freescale Semiconductor 5
1.4 PIN FUNCTION DESCRIPTIONS
1.4.1 V
CC
This pin supplies power to the device. Careful printed wiring board layout and capacitor placement is critical to ensure best per-
formance. An external bypass capacitor between this pin and V
SS
is required, as described in Section 1.5.
1.4.2 V
SS
This pin is the power supply return node for the digital circuitry on the MMA62XXEG device.
1.4.3 V
SSA
This pin is the power supply return node for analog circuitry on the MMA62XXAEG device. An external bypass capacitor between
this pin and V
CC
is required, as described in Section 1.5.
1.4.4 C
REG
This pin is connected to the internal digital circuitry power supply rail. An external filter capacitor must be connected between this
pin and V
SS
, as described in Section 1.5.
1.4.5 C
REGA
These pins are connected in parallel to the internal analog circuitry power supply rail. One or two external filter capacitors must
be connected between these pins and V
SSA
, as described in Section 1.5. Two pins are provided to support redundant connection
to the printed wiring board assembly. Redundant external capacitors may be connected to these pins for maximum reliability, as
described in Section 1.5.
1.4.6 C
REF
These pins are connected in parallel to an internal reference voltage node utilized by the analog circuitry. One or two external
filter capacitors must be connected between these pins and V
SSA
, as described shown in Section 1.5. Two pins are provided to
support redundant connection to the printed wiring board assembly. Redundant external capacitors may be connected to these
pins for maximum reliability, as described in Section 1.5.
1.4.7 VPP
This pin should be tied directly to V
SS
.
1.4.8 SCLK
This input pin provides the serial clock to the SPI port. The state of this pin is also used as a qualifier for externally-controlled
reset. An internal pull-down device is connected to this pin. This input may be left unconnected unless it is desired to initiate de-
vice reset as described in Section 1.4.9.
1.4.9 CS/RESET
This pin provides two functions. When the SPI is enabled, this pin functions as the chip select input for the SPI port. The state of
the D
IN
pin during low-to-high transitions of SCLK is latched internally and D
OUT
is enabled when CS is at a logic low level.
This pin may also be used to initiate a hardware reset. If CS
is held low and SCLK is held high for 512 μs, the internal reset signal
is asserted.
An internal pull-up device is connected to this pin.
1.4.10 D
OUT
This pin functions as the serial data output for the SPI port.
Immediately following device reset, D
OUT
is placed in a high impedance state for approximately 800 μs. At the end of this time,
D
OUT
is driven high and a 3ms stabilization delay required by the internal circuitry begins. Reset is reported by the device so the
system can be aware of potential difficulties if unexpected resets occur.
1.4.11 D
IN
This pin functions as the serial data input to the SPI.
