MMA6222EG
Sensors
Freescale Semiconductor 25
The response to a SPI error condition is shown below.
Figure 4-16 SPI Error Response
4.1.13 Initial Response
During initialization phase one, the device does not respond to SPI access attempts. During the second initialization phase, reg-
ister operations complete normally, however the device will respond to sensor data requests with No Data (ND) status. The first
acceleration request following completion of device initialization will also result in a No Data response. This ensures that an un-
expected reset will always be detectable, even in systems which poll the device at longer intervals than required for device ini-
tialization.
4.2 ERROR CONDITIONS
A number of error conditions may be detected. If an error condition is detected, MMA62XXEG will always transmit an error indi-
cator in place of acceleration data. Error indicators are defined in the following sections.
4.2.1 Error Condition Classification
Error conditions fall into five classes, as described below.
4.2.1.1 Critical Errors
Error condition affects device operation. Critical errors are always reported regardless of other error conditions which may be
detected.
4.2.1.2 Initialization
Initialization is a special case condition which occurs after reset until internal circuitry is ready to provide accurate acceleration
results. The duration of the initialization period depends upon whether a high-pass filter has been selected or not. If no high-pass
filter has been selected, initialization requires approximately 3 ms after power-up. If a high-pass filter has been selected, an ad-
ditional 200 ms is required. During the device initialization period, this status is reported in response to any acceleration data
request, however normal register access operations may be performed.
Device initialization status is cleared automatically.
4.2.1.3 Reset
Reset is also a special case condition. Reset will occur at power-on, as the result of a temporary undervoltage condition, or in
response to explicit actions taken by the controller. Upon negation of the internal reset signal, the DEVRES flag in the device
status (DEVSTAT) register is set. Because it is critically important that the system can detect any unintended reset condition, this
flag may only be cleared by writing a logic ‘1’ to the CE bit in the device control register (DEVCTL) after device initialization has
completed.
4.2.1.4 Transient Errors
An error condition which may be the result of a condition which precludes an accurate acceleration measurement but which may
not persist. Transient errors are reported in response to acceleration data transfer requests. If a transient error condition has been
detected, a logic ‘1’ may be written to the clear error (CE) bit in the device control (DEVCTL) register to clear the associated flag.
Should the error condition still exists, the flag will only be cleared momentarily.
0
SCLK
BIT
D
OUT
CS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00P0111000 100 00
