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MMA6222EG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
MMA6222EG
Sensors
28 Freescale Semiconductor
Table 4-5 Nominal Signed Acceleration Data Values
Digital
Value
Nominal Acceleration
10-Bit Range (Self Test Disabled)
20 g 35 g 50 g 100 g
511 Reserved
510 Overflow
509 Overrange
508 +20.8 +36.4 +52.0 +104
507 +20.8 +36.4 +51.9 +104
506 +20.7 +36.3 +51.8 +104
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
127 +5.20 9.11+ +13.0 +26.0
126 +5.16 +9.03 +12.9 +25.8
125 +5.12 +8.96 +12.8 +25.6
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3 +0.123 +0.215 +0.307 +0.614
2 +0.082 +0.143 +0.205 +0.410
1 +0.041 +0.072 +0.102 +0.205
0 0 0 0 0
-1 -0.041 -0.072 -0.102 -0.205
-2 -0.082 -0.143 -0.205 -0.410
-3 -0.123 -0.215 -0.307 -0.614
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
-126 -5.16 -9.03 -12.9 -25.8
-127 -5.20 -9.11 -13.0 -26.0
-128 -5.24 -9.18 -13.1 -26.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
-507 -20.8 -36.4 -51.9 -104
-508 -20.8 -36.4 -52.0 -104
-509 -20.9 -36.5 -52.1 -104
-510 Underrange
-511 Underflow
-512 Reserved
MMA6222EG
Sensors
Freescale Semiconductor 29
4.3.1 Overrange Response
Positive acceleration levels which exceed the full-scale range of the device fall into two categories: overrange and overflow. Over-
range conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits of the
DSP. An overflow condition occurs if the output of the low-pass filter equals or exceeds the maximum digital value which can be
output from the sinc filter. Sinc filter saturation will occur before the internal datapath width is exceeded. At 25°C the sinc filter will
not saturate at sustained acceleration levels with the range of ±200 g. The DSP operates predictably under all cases of over-
range, although the signal may include residual high frequency components for some time after returning to the normal range of
operation due to non-linear effects of the sensor. If an overflow condition occurs, the signal is internally clipped. The DSP will
recover from an overflow condition within a few sample times after the input signal returns to the input range of the DSP. Due to
internal clipping within the DSP, some high-frequency artifacts may be present in the output following an overflow condition.
For negative acceleration levels, corresponding underrange and underflow conditions are defined.
4.4 CAP/HOLD INPUT
The CAP/HOLD input provides a system-level synchronization mechanism. When driven high, transfer of acceleration results
from the DSP to the SPI buffers does not occur. The DSP continues its normal operation regardless of the state of CAP/HOLD.
Data read from the device when CAP/HOLD is high will reflect the last values available from the DSP at the time of the signal
transition.
MMA6222EG
Sensors
30 Freescale Semiconductor
SECTION 5 OPERATING MODES
MMA62XXEG operates in one of two modes, factory test programming mode and normal operating mode. Factory test and pro-
gramming mode is entered only when certain conditions are met, and provides support for programming of customer-defined
data. Normal mode is entered by default when the device is powered on.
5.1 NORMAL OPERATING MODE
Normal mode is entered whenever the device is powered and the V
PP
pin is held at or below the level of V
CC
. In normal mode,
acceleration data and device support data transfers are supported.
5.1.1 Power-On Reset
Upon application of voltage at the V
CC
pin, the internal regulators will begin driving the internal power supply rails. The C
REG
and
C
REGA
pins are tied to the internal rails. As voltages at V
CC
, C
REG
and C
REGA
rise, the device becomes operational. An internal
reset signal is asserted at this time. Separate comparators on monitor all three voltages, and when all are above specified thresh-
olds, the reset signal is negated and the device begins its initialization process.
5.1.2 Device Initialization
Following any reset, the device completes a sequence of operations which initialize internal circuitry. Device initialization is com-
pleted in two phases. During the first phase, the fuse array is read and its contents are transferred to mirror registers. Power to
the fuse array is then removed to reduce supply current load. A voltage reference used within the sensor interface stabilizes dur-
ing the second phase. If the HPFSEL bit is set in the DSP configuration register (DSPCFG), the high-pass filter is also initialized
during phase two.
The device will not respond to SPI accesses during initialization phase one. Acceleration results are not available during initial-
ization phase two, however the SPI is functional and register operations may be performed. If an acceleration data access is
attempted, the device will respond with non-acceleration data.
The first initialization phase requires approximately 800 μs to complete. The second phase completes in approximately 3 ms if
no high-pass filter is selected, and 200 ms if the HPFSEL bit is programmed to a logic ‘1’ state. The DEVINIT bit in the device
status register (DEVSTAT) remains set following reset until the second phase of device initialization completes.
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MMA6222EG

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Accelerometers XY 20 / 20 DIGITAL
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