LTC4269-2
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A silicon diode bridge can consume over 4% of the available
power in some PD applications. Using Schottky diodes can
help reduce the power loss with a lower forward voltage.
A Schottky bridge may not be suitable for some high
temperature PD applications. The leakage current has
a temperature and voltage dependency that can reduce
the perceived signature resistance. In addition, the IEEE
802.3af/at specification mandates the leakage back-feeding
through the unused bridge cannot generate more than 2.8V
across a 100k resistor when a PD is powered with 57V.
Sharing Input Diode Bridges
At higher temperatures, a PD design may be forced to
consider larger bridges in a bigger package because the
maximum operating current for the input diode bridge is
drastically derated. The larger package may not be accept-
able in some space-limited environments.
One solution to consider is to reconnect the diode bridges
so that only one of the four diodes conducts current in
each package. This configuration extends the maximum
operating current while maintaining a smaller package
profile. Figure 7 shows how the reconnect the two diode
bridges. Consult the diode bridge vendors for the de-rating
curve when only one of four diodes is in operation.
Input Capacitor
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1µF capacitor (C14 in Figure 7) is used to
meet this AC impedance requirement. Place this capacitor
as close to the LTC4269-2 as possible.
Transient Voltage Suppressor
The LTC4269-2 specifies an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can
routinely see excessive peak voltages. To protect the
LTC4269-2, install a transient voltage suppressor (D3)
between the input diode bridge and the LTC4269-2 as close
to the LTC4269-2 as possible as shown in Figure 7.
Classification Resistor (R
CLASS
)
The R
CLASS
resistor sets the classification load current,
corresponding to the PD power classification. Select the
value of R
CLASS
from Table 2 and connect the resistor
between the R
CLASS
and V
PORTN
pins as shown in Figure 4,
or float the R
CLASS
pin if the classification load current is
not required. The resistor tolerance must be 1% or better
to avoid degrading the overall accuracy of the classifica-
tion circuit.
Load Capacitor
The IEEE 802.3af/at specification requires that the PD
maintains a minimum load capacitance of 5µF and does
not specify a maximum load capacitor. However, if the
load capacitor is too large, there may be a problem with
inadvertent power shutdown by the PSE.
This occurs when the PSE voltage drops quickly. The input
diode bridge reverses bias, and the PD load momentarily
powers off the load capacitor. If the PD does not draw
power within the PSE’s 300ms disconnection delay, the
PSE may remove power from the PD. Thus, it is necessary
to evaluate the load current and capacitance to ensure that
an inadvertent shutdown cannot occur.
The load capacitor can store significant energy when fully
charged. The PD design must ensure that this energy is not
inadvertently dissipated in the LTC4269-2. For example,
if the V
PORTP
pin shorts to V
PORTN
while the capacitor
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4269-2.
T2P Interface
When a 2-event classification sequence successfully
completes, the LTC4269-2 recognizes this sequence,
and provides an indicator bit, declaring the presence of
a
T
ype 2 PSE. The open-drain output provides the option
to use this signal to communicate to the LTC4269-2 load,
or to leave the pin unconnected.
Figure 8 shows two interface options using the T2P
pin and the opto-isolator. The T2P pin is active low and
connects to an optoisolater to communicate across the
applicaTions inForMaTion
