LTC4269-2
5
42692fb
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C.
PARAMETER CONDITIONS MIN TYP MAX UNITS
SOUT High Level I
GATE
= –25mA, V
IN
= 12V COMP = 2.5V, FB = 1V 10 V
SOUT Active Pull-Off in Shutdown V
IN
= 5V, SD_V
SEC
= 0V, SOUT = 1V 1 mA
SOUT to OUT (Rise) DELAY (t
DELAY
) COMP = 2.5V, FB = 1V (Note 16)
R
DELAY
= 120k
40
120
ns
ns
V
DELAY
0.9 V
OUT Driver
OUT Rise Time FB = 1V, C
L
= 1nF (Notes 15, 16) 50 ns
OUT Fall Time FB = 1V, C
L
= 1nF (Notes 15, 16) 30 ns
OUT Clamp Voltage I
GATE
= 0µA, COMP = 2.5V, FB = 1V 11.5 13 14.5 V
OUT Low Level I
GATE
= 20mA
I
GATE
= 200mA
0.45
1.25
0.75
1.8
V
V
OUT High Level I
GATE
= –20mA, V
IN
= 12V COMP = 2.5V, FB = 1V
I
GATE
= –200mA, V
IN
= 12V COMP = 2.5V, FB = 1V
9.9
9.75
V
V
OUT Active Pull-Off in Shutdown V
IN
= 5V, SD_V
SEC
= 0V, OUT = 1V 20 mA
OUT Max Duty Cycle COMP = 2.5V, FB = 1V, R
DELAY
= 10k (f
OSC
= 200kHz),
V
IN
= 10V, SD_V
SEC
= 1.4V, SS_MAXDC = V
REF
83 90 %
OUT Max Duty Cycle Clamp COMP = 2.5V, FB = 1V, R
DELAY
= 10k (f
OSC
= 200kHz),
V
IN
= 10V
SD_V
SEC
= 1.32V, SS_MAXDC = 1.84V
SD_V
SEC
= 2.64V, SS_MAXDC = 1.84V
63.5
25
72
33
80.5
41
%
%
Soft-Start
SS_MAXDC Low Level: V
OL
I
SS_MAXDC
= 150µA, OC = 1V 0.2 V
SS_MAXDC Soft-Start Reset Threshold Measured on SS_MAXDC 0.45 V
SS_MAXDC Active Threshold FB + 1V, DC > 0% 0.8 V
SS_MAXDC Input Current
(Soft-Start Pull-Down: I
DIS
)
SS_MAXDC = 1V, SD_V
SEC
= 1.4V, OC = 1V 800 µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Pins with 100V absolute maximum guaranteed for T ≥ 0°C,
otherwise 90V.
Note 3: PWRGD voltage clamps at 14V with respect to V
NEG
.
Note 4: In applications where the V
IN
pin is supplied via an external RC
network from a system V
IN
> 25V, an external Zener with clamp voltage
V
IN ON(MAX)
< V
Z
< 25V should be connected from the V
IN
pin to GND.
Note 5: All voltages are with respect to V
PORTN
pin unless otherwise noted.
Note 6: Input voltage specifications are defined with respect to LTC4269-2
pins and meet IEEE 802.3af/at specifications when the input diode bridge
is included.
Note 7: Signature resistance is measured via the ∆V/∆I method with the
minimum ∆V of 1V. The LTC4269-2 signature resistance accounts for the
additional series resistance in the input diode bridge.
Note 8: An invalid signature after the 1st classification event is mandated
by IEEE 802.3at standard. See the Applications Information section.
Note 9: Class accuracy is respect to the ideal current defined as
1.237/R
CLASS
and does not include variations in R
CLASS
resistance.
Note 10: This parameter is assured by design and wafer level testing.
Note 11: Voltages are with respect to GND unless otherwise specified.
Tested with COMP open, V
FB
= 1.4V, R
ROSC
= 178k, V
SYNC
= 0V, V
SS(MAXDC)
set to V
REF
(but electrically isolated), C
VREF
= 0.1µF, V
SD_VSEC
= 2V, R
BLANK
= 121k, R
DELAY
= 121k, V
ISENSE
= 0V, V
OC
= 0V, C
OUT
= 1nF, V
IN
= 15V,
SOUT open, unless otherwise specified.
Note 12: Guaranteed by correlation to static test.
Note 13: V
IN
start-up current is measured at V
IN
= V
IN(ON)
– 0.25V and
scaled by × 1.18 (to correlate to worst-case V
IN
start-up current at V
IN(ON)
.
Note 14: Maximum recommended SYNC frequency = 500kHz.
Note 15: Guaranteed but not tested.
Note 16: Timing for R = 40k derived from measurement with R = 240k.
