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LTC6802IG-2#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
LTC6802-2
16
68022fa
(logic high) for polling commands. All interface pins are
voltage mode, with voltage levels sensed with respect to
the V
–
supply. See Figure 1.
Data Link Layer
Clock Phase And Polarity: The LTC6802-2 SPI compat-
ible interface is configured to operate in a system using
CPHA = 1 and CPOL = 1. Consequently, data on SDI must
be stable during the rising edge of SCKI.
Data Transfers: Every byte consists of 8 bits. Bytes are
transferred with the most significant bit (MSB) first. On a
write, the data value on SDI is latched into the device on
the rising edge of SCKI (Figure 6). Similarly, on a read,
the data value output on SDO is valid during the rising
edge of SCKI and transitions on the falling edge of SCKI
(Figure 7).
CSBI must remain low for the entire duration of a com-
mand sequence, including between a command byte and
subsequent data. On a write command, data is latched in
on the rising edge of CSBI.
After a polling command has been entered, the SDO output
will immediately be driven by the polling state, with the
SCKI input ignored (Figure 8). See the Toggle Polling and
Level Polling sections.
Network Layer
Broadcast Commands: A broadcast command is one to
which all devices on the bus will respond, regardless of
device address. See the Bus Protocols and Commands
sections.
applicaTions inForMaTion
Table 1. Monitor Mode Cell Selection
WDTB GPIO2 GPIO1 CELL INPUTS MONITORED
0 0 0 Cells 1 to 5
0 0 1 Cells 1 to 6
0 1 0 Cells 1 to 7
0 1 1 Cells 1 to 8
1 0 0 Cells 1 to 9
1 0 1 Cells 1 to 10
1 1 0 Cells 1 to 11
1 1 1 Cells 1 to 12
If MMB is low then brought high, all device configuration
values are reset to the default states including the VUV,
VOV, and CDC configuration bits.
S
ERIAL
PORT
Overview
The LTC6802-2 has an SPI bus compatible serial port.
Devices can be connected in parallel, using digital isolators.
Multiple devices are uniquely identified by a part address
determined by the A0 to A3 pins.
Physical Layer
On the LTC6802-2, four pins comprise the serial interface:
CSBI, SCKI, SDI and SDO. The SDO and SDI may be tied
together, if desired, to form a single, bidirectional port.
Four address pins (A0 to A3) set the part address for ad-
dress commands. The TOS pin designates the top device
CSBI
SCKI
SDI
MSB (CMD) BIT6 (CMD) LSB (CMD)
LSB (DATA)
MSB (DATA)
68022 F06
Figure 6. Transmission Format (Write)
LTC6802-2
17
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applicaTions inForMaTion
With broadcast commands all devices can be sent com-
mands simultaneously. This is useful for A/D conversion
and polling commands. It can also be used with write
commands when all parts are being written with the same
data. Broadcast read commands should not be used in
the parallel configuration.
Address Commands: An address command is one in
which only the addressed device on the bus responds.
The first byte of an address command consists of 4 bits
with a value of 1000 and 4 address bits. The second byte
is the command byte. See the Bus Protocols and Com-
mands section.
PEC Byte: The packet error code (PEC) byte is a CRC
value calculated for all of the bits in a register group in
the order they are read, using the following characteristic
polynomial:
x
8
+ x
2
+ x + 1
On a read command, after sending the last byte of a reg-
ister group, the device will shift out the calculated PEC,
MSB first.
Toggle Polling: Toggle polling allows a robust determina-
tion both of device states and of the integrity of the con-
nections between the devices in a stack. Toggle polling
CSBI
SCKI
SDI
SDO
MSB (CMD) BIT6 (CMD) LSB (CMD)
LSB (DATA)
MSB (DATA)
68022 F07
Figure 7. Transmission Format (Read)
Figure 8. Transmission Format (Poll)
CSBI
SCKI
SDI
SDO
POLL STATE
MSB (CMD) BIT6 (CMD) LSB (CMD)
68022 F08
LTC6802-2
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applicaTions inForMaTion
is enabled when the LVLPL bit is low. After entering a
polling command, the data out line will be driven by the
slave devices based on their status. When polling for the
A/D converter status, data out will be low when any device
is busy performing an A/D conversion and will toggle at
1kHz when no device is busy. Similarly, when polling for
interrupt status, the output will be low when any device
has an interrupt condition and will toggle at 1kHz when
none has an interrupt condition.
Toggle Polling—Address Polling: The addressed device
drives the SDO line based on its state alone—low for
busy/in interrupt, toggling at 1kHz for not busy/not in
interrupt.
Toggle Polling—Parallel Broadcast Polling: No part
address is sent, so all devices respond simultaneously.
If a device is busy/in interrupt, it will pull SDO low. If a
device is not busy/not in interrupt, then it will release the
SDO line (TOS = 0) or attempt to toggle the SDO line at
1kHz (TOS =1).
The master controller pulls CSBI high to exit polling.
Level polling: Level polling is enabled when the LVLPL
bit is high. After entering a polling command, the data
out line will be driven by the slave devices based on their
status. When polling for the A/D converter status, data
out will be low when any device is busy performing an
A/D conversion and will be high when no device is busy.
Similarly, when polling for interrupt status, the output will
be low when any device has an interrupt condition and will
be high when none has an interrupt condition.
Level polling—Address Polling: The addressed device
drives the SDO line based on its state alone—pulled low for
busy/in interrupt, released for not busy/not in interrupt.
Level polling—Parallel Broadcast Polling: No part address
is sent, so all devices respond simultaneously. If a device
is busy/in interrupt, it will pull SDO low. If a device is not
busy/not in interrupt, then it will release the SDO line. If
any device is busy or in interrupt the SDO signal will be
low. If all devices are not busy/not in interrupt, the SDO
signal will be high.
The master controller pulls CSBI high to exit polling.
Polling Methods: For A/D conversions, three methods can
be used to determine A/D completion. First, a controller can
start an A/D conversion and wait for the specified conver-
sion time to pass before reading the results. The second
method is to hold CSBI low after an A/D start command
has been sent. The A/D conversion status will be output
on SDO. A problem with the second method is that the
controller is not free to do other serial communication
while waiting for A/D conversions to complete. The third
method overcomes this limitation. The controller can send
an A/D start command, perform other tasks, and then
send a Poll A/D Converter Status (PLADC) command to
determine the status of the A/D conversions.
For OV/UV interrupt status, the poll interrupt status (PLINT)
command can be used to quickly determine whether
any cell in a stack is in an overvoltage or undervoltage
condition.
Bus Protocols
There are 6 different protocol formats, depicted in Table 3
through Table 8. Table 2 is the key for reading the protocol
diagrams.
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LTC6802IG-2#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Battery Stack Monitor, Individually Addressable SPI
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