Rev. Issue Date Intiator Description Page #
A 8/15/2012 RDW
1. Changed Description, Recommended Application and DS title to say
"Clock Generator" instead of "Frequency Generator"
2. Changed Output Features text. Updated block diagram to highlight
internal terminations.
3. Highlighted the standby power pins in the pinout (pins 4,5,8)
4. Added footnote 1 to Power Management Table
5. Cleaned up the Test Load Diagrams and merged with Alternate
Terminations Diagram.
6. Updated electrical tables with char data, removed "Clock Periods-
Single-ended Outputs" table which was redundant. Updated footnote
two on Clock Periods Table.
7. Changed integration range for phase jitter calculation of REF from
"12kHz to 20MHz" to "12kHz to 5MHz"
8. Corrected Byte 6
9. Added Thermal Data and Recommended Crystal tables
10. Move to final.
1,2,4,5-
8,11-13
B 12/19/2012 AT
1. Added SADR column to SMBus Address Selection table.
2. Changed VIH min. from 0.65*VDD to 0.75*VDD, VIM min. from
0.35*VDD to 0.4*VDD and max. from 0.65*VDD to 0.6*VDD, and VIL
max. from 0.35*VDD to 0.25*VDD
2,6
C 7/24/2103 RDW
1. Minor updates to electrical characterisitcs per additional char data.
2. Idd reduced for 9FGV0241
3. Slew rate parameters for each setting for REF output added to table.
4. Typical values updated.
5. Changed descriptions of Byte 3, bits 7:6 to "Slowest, Slow, Fast,
Faster, since actual values are now included in the REF Electrical
Table.
5-8,10
D 9/10/2014 RDW
Updated Ordering Information/Shipping Pacakging from "Trays" to
"Tubes".
13
E 2/3/2015 RDW
Updated IDDAOP and IDDOP typ and max specs per latest
characterization review.
5
F 11/30/2015 RDW Updated block diagram 1
G
1/4/2016 RDW Corrected typo in ordering information; changed rev "B" to rev "A" 13
H 10/18/2016 RDW Removed IDT crystal part number
