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9FGV0241AKLF

P1-P3P4-P6P7-P9P10-P12P13-P15
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR 7
9FGV0241 OCTOBER 18, 2016
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
Electrical Characteristics–Phase Jitter Parameters
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Scope avera
g
in
g
on 3.0V/ns settin
g
23.14.3
V/ns
1, 2, 3
Scope avera
g
in
g
on 2.0V/ns settin
g
1.5 2.3 3.5
V/ns
1, 2, 3
Slew rate matching
Δ
Trf Slew rate matching, Scope averaging on
3
20
%
1,2,4
Voltage High V
HIGH
660
794
850 1,7
Voltage Low V
LOW
-150
21
150 1
Max Voltage Vmax
816
1150 1
Min Voltage Vmin -300
-15
1
Vswing Vswing Scope averaging off 300
1551
mV 1,2
Crossin
g
Volta
g
e (abs) Vcross_abs Scope avera
g
in
g
off 300
397
550 mV 1,5
Crossing Voltage (var)
Δ
-Vcross Scope averaging off
15
140 mV 1,6
2
Measured from differential waveform
7
At default SMBus settings.
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
Slew rate Trf
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting
∆
-Vcross to be smaller than Vcross absolute.
1
Guaranteed by design and characterization, not 100% tested in production.
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
INDUSTRY
LIMIT UNITS NOTES
t
jphPCIeG1
PCIe Gen 1 202535 86
ps
(p-p)
1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.8 0.9 1.1 3
ps
(rms)
1,2,5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
1.5
1.6
1.9 3.1
ps
(rms)
1,2,5
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.33
0.37
0.50 1
ps
(rms)
1,2,4,5
1
Guaranteed by design and characterization, not 100% tested in production.
5
Applies to all differential outputs
4
Calculated from Intel-supplied Clock Jitter Tool
Phase Jitter, PCI Express t
jphPCIeG2
2
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR 8
9FGV0241 OCTOBER 18, 2016
Electrical Characteristics–REF
Clock Periods–Differential Outputs with Spread Spectrum Disabled
Clock Periods–Differential Outputs with -0.5% Spread Spectrum Enabled
TA = T
COM
or T
IND
; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values ppm 1,2
Clock period T
p
eriod
25 MHz output nominal 40 ns 1,2
Rise/Fall Slew Rate t
rf1
Byte 3 = 1F, V
OH
= VDD-0.45V, V
OL
= 0.45V 0.5 1 2.5 V/ns 1,3
Rise/Fall Slew Rate t
rf1
Byte 3 = 5F, V
OH
= VDD-0.45V, V
OL
= 0.45V 0.5 1.6 2.5 V/ns 1,3
Rise/Fall Slew Rate t
rf1
Byte 3 = 9F, V
OH
= VDD-0.45V, V
OL
= 0.45V 0.5 2 2.5 V/ns 1,3
Rise/Fall Slew Rate t
rf1
Byte 3 = DF, V
OH
= VDD-0.45V, V
OL
= 0.45V 0.5 2.1 2.5 V/ns 1,3
Duty Cycle d
t1
V
T
= VDD/2 V 45 53.1 55 % 1,4
Duty Cycle Distortion d
tcd
V
T
= VDD/2 V 0 2 4 % 1,5
Jitter, cycle to cycle t
j
c
y
c-c
y
c
V
T
= VDD/2 V 19 250 ps 1,4
Noise floor t
j
dBc1k
1kHz offset -130 -105 dBc 1,4
Noise floor t
j
dBc10k
10kHz offset to Nyquist -140 -120 dBc 1,4
Jitter, phase t
jphREF
12kHz to 5MHz 0.63 1.5
ps
(rms)
1,4
1
Guaranteed by design and characterization, not 100% tested in production.
3
Typical value occurs when REF slew rate is set to default value
4
When driven by a crystal.
5
When driven by an external oscillator via the X1 pin. X2 should be floatin
g
in this case.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
0
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2
Notes
Measurement Window
UnitsSSC OFF
Center
Freq.
MHz
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
Notes
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR 9
9FGV0241 OCTOBER 18, 2016
General SMBus Serial Interface Information
How to Write
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Note: Read/Write address is determined by SADR latch.
How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
O O
O O
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N Not acknowledge
PstoP bit
P1-P3P4-P6P7-P9P10-P12P13-P15

9FGV0241AKLF

Mfr. #:
Buy 9FGV0241AKLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products PCIe CLOCK GENERATOR GEN 1/2/3, 2 OUT
Lifecycle:
New from this manufacturer.
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