General description STA020
10/15 DocID006832 Rev 7
indicates audio/non-audio; C6 and C7 determine the sample frequency and C9 allows the
encoded channel mode to be stereophonic. EM1 and EM0 determine emphasis and encode
C2, C3, C4 as shown in Table 6. The dedicated channel status pins are read at the
appropriate time and are logically OR’ed with data input on the channel status port, C. In
transparent mode, these dedicated channel status pins are ignored and channel status bits
are input at the C pin.
2.7 Consumer mode
Setting PRO high places the STA020 in consumer mode which redefines the pins as shown
in Figure 9. In consumer mode, channel status bit 0 is transmitted as a zero and channel
status bits 2, 3, 8, 9, 15, 24 and 25 are controlled via dedicated pins.
The pins are actually the inverse of the bit so if pin C2 is tied high, channel status bit 2 will
be transmitted as a zero. Also, FC0 and FC1 are encoded versions of channel status bits 24
and 25, which define the sample frequency.
When FC0 and FC1 are both high, the part is placed in a CD submode which activates the
CD subcode port. This submode is described in detail in the next section. Table 7 describes
the encoding of C24 and C25 through the FC1 and FC0 pins. According to AES/EBU
standards, C2 is copy prohibit/permit. C3 specifies pre-emphasis, C8 and C9 define the
category code and C15 identifies the generation status of the transmitted material (i.e. first
generation, second generation).
Table 6. Emphasis encoding
Table 7. Sample frequency encoding
EM1 EM0 C2 C3 C4
00111
01110
10100
11000
FC1 FC0 C24 C25 Comments
0 0 0 0 44.1 kHz
0 1 0 1 48 kHz
1 0 1 1 32 kHz
1 1 0 0 44.1 kHz, CD mode
DocID006832 Rev 7 11/15
STA020 General description
15
Figure 7. Transparent mode interface
Figure 8. Block diagram - professional mode
MCK
CBL
C
U
V
FSYNC
DATA
PROCESSING
RXP
RXN
SCK
STA120
STA020
TXN
TXP
TRNPT
V+
D97AU605
SDATA
SERIAL
PORT
LOGIC
REGISTERS
M0 M1
M2
23 22
21
AUDIO
AUX
C Bits
U Bits
VALIDITY
PREAMBLE
PARITY
SDATA
8
SCK
6
FSYNC
7
C
10
U
11
V
9
MUX
BIPHASE
MARK
ENCODER
LINE
DRIVER
TIMING
2141334112 15 5
16
17
20
EM0 EM1 C1 C6 C7 C9 CBL MCK
PRO
RST
TXN
TXP
D97AU607B
TRNPT
24
MUX
CRC
General description STA020
12/15 DocID006832 Rev 7
Figure 9. Block diagram - consumer mode
SERIAL
PORT
LOGIC
REGISTERS
M0 M1
M2
23 22
21
AUDIO
AUX
C Bits
U Bits
VALIDITY
PREAMBLE
PARITY
SDATA
8
SCK
6
FSYNC
7
C
10
U
11
V
9
MUX
BIPHASE
MARK
ENCODER
LINE
DRIVER
TIMING
2
+3.3V
324 4 1131412 15 5
16
17
20
FC0 FC1 C2 C3 C8 C9 C15 CBL MCKPRO
RST
TXN
TXP
D97AU606A
MUX

STA020DJTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Audio Transmitters, Receivers, Transceivers 96kHz Digital Audio CMOS Interface
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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