General description STA020
8/15 DocID006832 Rev 7
2.3 C, U, V serial port
The serial input pins for channel status (C), user (U), and validity (V) are sampled during the
first bit period after the active edge of FSYNC for all formats except Format 4. Format 4 is
sampled during the second bit period (coincident with the MSB). In Figure 5, the arrows on
SCK indicate when the C, U, and V bits are sampled. The C, U, and V bits are transmitted
with the audio sample entered before FSYNC edge that sampled it. The V bit, as defined in
the audio standards, is set to zero to indicate the audio data is suitable for conversion to
analog. Therefore, when the audio data is errored, or the data is not audio, the V bit should
be set high. The channel status serial input pin (C) is not available in consumer mode when
the CD subcode port is enabled (FC1 = FC0 = high). Any channel status data entered
through the channel status serial input (C) is logically OR’ed with the data entered through
the dedicated pins or internally generated.
2.4 RST and CBL (TRNPT is low)
When RST goes low, the differential line drivers are set to ground. In order to properly
synchronize the STA020 to the audio serial port, the transmit timing counters, which include
CBL, are not enabled after RST goes high until eight and one half SCK periods after reset is
exited) of FSYNC. When FSYNC is configured as a left/right signal (all defined formats
except 2), the counters and CBL are not enabled until the right sample is being transmitted).
This guarantees that channel A is left and channel B is right as per the digital audio interface
specs.
As shown in Figure 4, channel block start output (CBL) can assist in serially inputting the C,
U and V bits as CBL goes high one bit period before the first bit of the preamble of the first
sub-frame of the channel status block is transmitted. This sub-frame contains channel
status byte 0, bit 0. CBL returns low one bit period before the start of the frame that contains
bit 0 of channel status byte 16. CBL is not available when the CD subcode port is enabled.
Figure 4 illustrates timing for stereo data input on the audio port. Notice how CBL rises while
the right channel data (Right 0) is input, but the previous left channel (Left 0) is being
transmitted as the first sub-frame of the channel status block (starting with preamble Z). The
C, U, and V input ports only need to be valid for a short period after FSYNC changes. A sub-
frame includes one audio sample while a frame includes a stereo pair. A channel status
(C.S.) block contains 24 bytes of channel status and 384 audio samples (or 192 stereo
pairs, or frames, of samples). Figure 4 shows the CUV ports as having left and right bits
(e.g. CUV0L, CUV0R). Since the C.S. block is defined as 192 bits, or one bit per frame,
there are actually 2 C.S. blocks, one for channel A (left) and one for channel B (right). When
inputting stereo audio data, both blocks normally contain the same information, so C0L and
C0R from the input port pin are both channel status bit 0 of byte 0, which is defined as
professional/consumer. These first two bits from the port, C0L and C0R, are logically OR’ed
with the inverse
PRO, since PRO is a dedicated channel status pin defined as C.S. bit 0.
Also, if in professional mode, C1, C6, C7 and C9 are dedicated C.S. pins. The inverse of C1
is logically OR’ed with channel status input ports bits C1L and C1R. In similar fashion, C6,
C7 and C9 are OR’ed with their respective input bits. Also, the C bits in CUV128L and
CUV128R are both channel status block bit 128, which is bit 0 of channel status byte 16.
