General description STA020
6/15 DocID006832 Rev 7
2 General description
The STA020 is a monolithic CMOS circuit that encodes and transmits audio and digital data
according to the AES/EBU, IEC 958, S/PDIF, and EIAJ CP-340 interface standards. The
chip accepts audio and control data separately; multiplex and biphase-mark encode the
data internally and drive it, directly or through a transformer, to a transmission line.
The STA020 has dedicated pins for the most important control bits and a serial input port for
the C, U and V bits.
The STA020 accepts 16 to 24-bit audio samples through a serial port configured in one of
seven formats; provides several pins dedicated to particular channel status bits and allows
all channel status, user and validity bits to be serially input through port pins. This data is
multiplexed, the parity bit is generated and the bit stream is biphase-mark encoded and
driven through an RS422 line driver.
The STA020 operates as a professional or consumer interface transmitter selectable by pin
2, PRO. As a professional interface device, the dedicated channel status input pins are
defined according to the professional standard, and the CRC code (C.S. byte 23) can be
internally generated.
As a consumer device, the dedicated channel status input pins are defined according to the
consumer standard. A submode provided under the consumer mode is compact disk, CD,
mode. When transmitting data from a compact disk, the CD subcode port can accept CD
subcode data, extract channel status information from it, and transmit it as user data.
The master clock, MCK, controls timing for the entire chip and must be 128xFs. As an
example, if stereo data is input to the STA020 at 44.1kHz, MCK input must be 128 times that
or 5.6448 MHz.
2.1 Line drivers
The differential line drivers for STA020 are low skew, low impedance, differential outputs
capable of driving 110 Ohm transmission lines. (RS422 line driver compatible).
They can also be disabled by resetting the device (RST = low).
2.2 Audio serial port
The audio serial port is used to enter audio data and consists of three pins: SCK, SDATA
and FSYNC, SCK clocks in SDATA, which is double buffered, while FSYNC delineates the
audio samples and may indicate the particular channel, left or right. To support many
different interfaces, M2, M1 and M0 select one of seven different formats for the serial port.
The coding is shown in Table 5 while the formats are shown in Figure 5.
Format 0 and 1 are designed to interface with crystal ADCs. Format 2 communicates with
Motorola and TI DSPs. Format 3 is reserved. Format 4 is compatible with the I
2
S standard.
Formats 5 and 6 make the STA020 look similar to existing 16- and 18-bit DACs and
interpolation filters. Format 7 is an MSB-last format and is conducive to serial arithmetic.
SCK and FSYNC are outputs in Format 0 and inputs in all other formats. In Format 2, the
rising edge of FSYNC delineates samples and the falling edge must occur a minimum of
one bit period before or after the rising edge. In all formats except 2, FSYNC contains
left/right information requiring both edges of FSYNC to delineate samples. Formats 5 and 6
