Document Number: 38-07246 Rev. *K Page 12 of 19
TTB Total timing budget
[9, 10]
,
Bank A and B same frequency
Outputs at 200 MHz, tracking skew
not included
– – 650 ps
Total timing budget,
Bank A and B different frequency
– – 850
t
5
Output to output skew
[11]
All outputs equally loaded – 35
[12]
200 ps
Bank to bank skew Same frequency – – 200
Bank to bank skew Different frequency – – 400
Bank to bank skew Different voltage, same frequency – – 400
t
6
Input to output skew
(static phase offset)
[11]
Measured at V
DD
/2, REF to FBK – 0 250 ps
t
7
Device-to-device skew
[11]
Measured at V
DD
/2 – 0 500 ps
t
J
Cycle-to-cycle jitter
[11]
(Peak) Banks A and B at same frequency – 110
[13]
200 ps
Cycle-to-cycle jitter
[11]
(Peak) Banks A and B at different
frequencies
– – 400
t
TSK
Tracking skew Input reference clock at < 50 KHz
modulation with ±3.75% spread
– – 200 ps
t
LOCK
PLL lock time
[11]
Stable power supply, valid clock at
REF
– – 1.0 ms
t
LD
Inserted loop delay Max loop delay for PLL Lock (stable
frequency)
– – 7 ns
Max loop delay to meet Tracking
Skew Spec
– – 4 ns
Switching Characteristics (continued)
Parameter
[6]
Description Test Conditions Min Typ Max Unit
Notes
9. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
10. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle
jitter, and dynamic phase error.TTB will be equal to or smaller than the maximum specified value at a given frequency.
11. All parameters are specified with loaded outputs.
12. Same frequency, 15 pF load, high drive.
13. Same frequency, 15 pF load, low drive.
