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CY23FP12OXC-003

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
CY23FP12
Document Number: 38-07246 Rev. *K Page 7 of 19
Tab l e 2 lists independent functions that can be assigned to each of the four S1 and S2 combinations. When a particular S1 and S2
combination is selected, the device assumes the configuration (which is essentially a set of functions given in Ta b le 2) that has been
preassigned to that particular combination.
Table 2. Programmable Functions for S1/S2 Combinations
Function Description Default
Output Enable CLKB[5:4] Enables/Disables CLKB[5:4] output pair See Table 4 on
page 8
Output Enable CLKB[3:2] Enables/Disables CLKB[3:2] output pair See Table 4 on
page 8
Output Enable CLKB[1:0] Enables/Disables CLKB[1:0] output pair See Table 4 on
page 8
Output Enable CLKA[5:4] Enables/Disables CLKA[5:4] output pair See Table 4 on
page 8
Output Enable CLKA[3:2] Enables/Disables CLKA[3:2] output pair See Table 4 on
page 8
Output Enable CLKA[1:0] Enables/Disables CLKA[1:0] output pair See Table 4 on
page 8
Auto Power-down Enable Enables/Disables the auto power down circuit, which monitors the reference clock rising
edges and shuts down the device in case of a reference “failure.” This failure is triggered
by a drift in reference frequency below a set limit. This auto power down circuit is disabled
internally when one or more of the outputs are configured to be driven directly from the
reference clock.
Enable
PLL Power-down Shuts down the PLL when the device is configured as a non-PLL fanout buffer. PLL Enabled
M[7:0] Assigns an eight-bit value to reference divider –M. The divider can be any integer value
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
2
N[7:0] Assigns an eight-bit value to feedback divider –N. The divider can be any integer value
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
2
X[6:0] Assigns a seven-bit value to output divider –X. The divider can be any integer value from
5 to 130. Divide by 1,2,3, and 4 are preprogrammed on the device and can be activated
by the appropriate output mux setting.
1
Divider Source Selects between the PLL output and the reference clock as the source clock for the output
dividers.
See Table 4 on
page 8
CLKA54 Source Independently selects one out of the eight possible output dividers that will connect to the
CLKA5 and CLKA4 pair. Please refer to Table 3 on page 8 for a list of divider values.
Divide by 2
CLKA32 Source Independently selects one out of the eight possible output dividers that will connect to the
CLKA3 and CLKA2 pair. Please refer to Table 3 on page 8 for a list of divider values.
Divide by 2
CLKA10 Source Independently selects one out of the eight possible output dividers that will connect to the
CLKA1 and CLKA0 pair. Please refer to Table 3 on page 8 for a list of divider values.
Divide by 2
CLKB54 Source Independently selects one out of the eight possible output dividers that will connect to the
CLKB5 and CLKB4 pair. Please refer to Table 3 on page 8 for a list of divider values.
Divide by 2
CLKB32 Source Independently selects one out of the eight possible output dividers that will connect to the
CLKB3 and CLKB2 pair. Please refer to Table 3 on page 8 for a list of divider values.
Divide by 2
CLKB10 Source Independently selects one out of the eight possible output dividers that will connect to the
CLKB1 and CLKB0 pair. Please refer to Table 3 on page 8 for a list of divider values.
Divide by 2
CY23FP12
Document Number: 38-07246 Rev. *K Page 8 of 19
Tab l e 3 is a list of output dividers that are independently selected
to connect to each output pair.
In the default (unprogrammed) state of the device, S1 and S2
pins will function as indicated in Ta b le 4 .
Field Programming the CY23FP12
The CY23FP12 must be programmed in a device programmer
prior to being installed in a circuit. The CY23FP12 is based on
flash technology, so it can be reprogrammed up to 100 times.
This enables fast and easy design changes and product
updates, and eliminates any issues with old and out-of-date
inventory.
Samples and small prototype quantities can be programmed on
the CY3672-USB programmer. Cypress’s value-added
distribution partners and third-party programming systems from
BP Microsystems, HiLo Systems, and others are available for
large production quantities.
CyberClocks Software
CyberClocks is an easy-to-use software application that allows
the user to custom-configure the CY23FP12. Users can specify
the REF frequency, PLL frequency, output frequencies and/or
post-dividers, and different functional options. CyberClocks
outputs an industry standard JEDEC file used for programming
the CY23FP12.
CyberClocks can be downloaded free of charge from the
Cypress website at www.cypress.com.
CY3672-USB Development Kit
The Cypress CY3672-USB Development Kit, in combination with
the CY3692 Socket Adapter, is used to program samples and
small prototype quantities of the CY23FP12. This portable
programmer connects to a PC via a USB interface.
CY23FP12 Frequency Calculation
The CY23FP12 is an extremely flexible clock buffer with up to
twelve individual outputs, generated from an integrated PLL.
Four variables are used to determine the final output frequency.
These are the input Reference Frequency, the M and N dividers,
and the post divider.
The basic PLL block diagram is shown in Basic PLL Block
Diagram on page 5. Each of the six clock output pairs has many
post divider options available to it. There are six post divider
options: /1, /2, /3, /4, /X, and /2X. X is a programmable value
between 5 and 130, and 2X is twice that value. The post divider
options can be applied to the calculated PLL frequency or to the
REF directly. The feedback is connected either internally to
CLKA0 or externally to any output.
A programmable divider, M, is inserted between the reference
input, REF, and the phase detector. The divider M can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
A programmable divider, N, is inserted between the feedback
input, FBK, and the phase detector. The divider N can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
The output can be calculated as follows:
F
REF
/ M = F
FBK
/ N.
F
PLL
= (F
REF
× N × post divider) / M.
F
OUT
= F
PLL
/ post divider.
In addition to above divider options, the following option
bypasses the PLL and passes the REF directly to the output.
F
OUT
= F
REF
.
Table 3. Output Dividers
CLKA/B Source Output Connects To
0 [000] REF
1 [001] Divide by 1
2 [010] Divide by 2
3 [011] Divide by 3
4 [100] Divide by 4
5 [101] Divide by X
6 [110] Divide by 2X
[1]
7 [111] TEST mode [LOCK signal]
[2]
Table 4. S1/S2 Default Functionality
S2 S1 CLKA[5:0] CLKB[5:0]
Divider
Source
0 0 Three-state Three-state PLL
0 1 Driven Three-state PLL
1 0 Driven Driven Reference
1 1 Driven Driven PLL
Notes
1. Outputs will be rising edge aligned only to those outputs using this same device setting.
2. When the source of an output pair is set to [111], the output pair becomes lock indicator signal. For example, if the source of an output pair (CLKA0, CLKA1) is set
to [111], the CLKA0 and CLKA1, becomes lock indicator signals. In non-invert mode, CLKA0 and CLKA1 signals will be high when the PLL is in lock mode. If CLKA0
is in an invert mode, the CLKA0 will be low and the CLKA1 will be high when the PLL is in lock mode.
CY23FP12
Document Number: 38-07246 Rev. *K Page 9 of 19
Absolute Maximum Conditions
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Parameter Description Condition Min Max Unit
V
DD
Supply voltage Non-functional –0.5 7 VDC
V
IN
Input voltage REF Relative to V
CC
–0.5 V
DD
+ 0.5 VDC
V
IN
Input voltage except REF Relative to V
CC
–0.5 V
DD
+ 0.5 VDC
LU
I
Latch-up immunity Functional 300 mA
T
S
Temperature, storage Non-functional –65 125 °C
T
J
Junction temperature – 125 °C
ESD
h
ESD protection (Human body
model)
2000 V
M
SL
Moisture sensitivity level MSL – 3 class
G
ATES
Total functional gate count Assembled Die 21375 each
UL–94 Flammability rating At 1/8 in. V–0 class
FIT Failure in time Manufacturing test 10 ppm
Operating Conditions
Parameter Description Test Conditions Min Max Unit
V
DDC
Core supply voltage 3.135 3.465 V
V
DDA
, V
DDB
Bank A, Bank B supply voltage 3.135 3.465 V
2.375 2.625 V
T
A
Temperature, operating ambient Commercial temperature 0 70 °C
Industrial temperature –40 85
t
PU
Power-up time for all V
DDs
to
reach minimum specified voltage
(power ramps must be
monotonic)
0.05 500 ms
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

CY23FP12OXC-003

Mfr. #:
Buy CY23FP12OXC-003
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 200MHz Field Program Zero Delay Buffer
Lifecycle:
New from this manufacturer.
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