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© 2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5711/3
AUGUST 2001
IDT72V70200
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
512 x 512
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc.
FUNCTIONAL BLOCK DIAGRAM
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
ODE
F0i
V
CC
CS
DS/
RD
R/W /
WR
A0-A7
GND
CCO
DTA
D8-D15/
AD0-AD7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
TX8
TX9
TX10
TX11
TX12
TX13
TX14
TX15
AS/
ALE
IM
CLK FE IC
TDITMS TCKTDO
TRSTRESET
IC
5711 drw01
Receive
Serial Data
Streams
Output
MUX
Loopback
Test Port
Data Memory
Internal
Registers
Microprocessor Interface
Timing Unit
Connection
Memory
Transmit
Serial Data
Streams
FEATURES:
• 512 x 512 channel non-blocking switching at 2.048 Mb/s
• Per-channel variable or constant throughput delay
• Automatic identification of ST-BUS
®
/GCI interfaces
• Accept 16 serial data streams of 2.048 Mb/s
• Automatic frame offset delay measurement
• Per-stream frame delay offset programming
• Per-channel high impedance output control
• Per-channel Processor Mode
• Control interface compatible to Intel/Motorola CPUs
• Connection memory block programming
• IEEE-1149.1 (JTAG) Test Port
• Available in 84-pin Plastic Leaded Chip Carrier (PLCC),
100-pin Ball Grid Array (BGA), 100-pin Plastic Quad Flatpack
(PQFP) and 100-pin Thin Quad Flatpack (TQFP)
• 3.3V Power Supply
• Operating Temperature Range -40
°°
°°
°C to +85
°°
°°
°C
DESCRIPTION:
The IDT72V70200 is a non-blocking digital switch that has a capacity of
512 x 512 channels at 2.048 Mb/s. Some of the main features are: program-
mable stream and channel control, Processor Mode, input offset delay and high-
impedance output control.
Per-stream input delay control is provided for managing large multi-chip
switches that transport both voice channel and concatenated data channels. In
addition, input streams can be individually calibrated for input frame offset.
100-pin Thin Quad Flatpack (TQFP)
