7
COMMERCIAL TEMPERATURE RANGE
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 5
12
CONNECTION MEMORY CONTROL
The CCO pin is a 4.096 Mb/s output, which carries 512 bits. The contents
of the CCO bit of each connection memory location are output on the CCO pin
once every frame. The contents of the CCO bits of the connection memory are
transmitted sequentially on to the CCO pin and are synchronous with the data
rates on the other serial streams.
The CCO bit is output one channel before the corresponding channel on
the serial streams. For example, the contents of the CCO bit in position 0 (TX0,
CH0) of the connection memory is output on the first clock cycle of channel 31
through CCO pin. The contents of the CCO bit in position 32 (TX1, CH0) of the
connection memory is output on the second clock cycle of channel 31 via CCO
pin.
If the ODE pin or the OSB bit is high, the OE bit of each connection memory
location controls the output drivers-enables (if high) or disables (if low). See
Table 4 for detail.
The processor channel (PC) bit of the connection memory selects between
Processor Mode and Connection Mode. If high, the contents of the connection
memory are output on the TX streams. If low, the stream address bit (SAB) and
the channel address bit (CAB) of the connection memory defines the source
information (stream and channel) of the time-slot that will be switched to the output
from data memory.
The V/C (Variable/Constant Delay) bit in each connection memory location
allows the per-channel selection between variable and constant throughput
delay modes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., RX n channel m data comes from the
TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.
INITIALIZATION OF THE IDT72V70200
After power up, the state of the connection memory is unknown. As such,
the outputs should be put in high impedance by holding the ODE low. While the
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.
8
COMMERCIAL TEMPERATURE RANGE
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 5
12
Connection Memory
Data Memory
1
0
Control Register
CR
b
7
5711 drw06
10000000
T
he Control Register is only accessed when A7-A0 are all
z
eroed. When A7 =1, up to 32 bytes are randomly accessable
v
ia A0-A4 at any one instant. Of which stream these
b
ytes (channels) are accessed is determined by the state of
C
R
b
3 -CR
b
0.
CR
b
6CR
b
5CR
b
4CR
b
2CR
b
1CR
b
0
CR
b
4
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111
7
Stream
CR
b
2CR
b
1CR
b
0
0
0
0
0
0
0
0
0
CR
b
3
CR
b
3
8
9
10
11
12
13
14
15
000
001
010
011
100
101
110
111
1
1
1
1
1
1
1
1
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
Channel 0 Channel 1 Channel 2
10000001 10000010
10011111
External Address Bits A7-A0
Figure 3. Addressing Internal Memories
9
COMMERCIAL TEMPERATURE RANGE
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 5
12
TABLE 2 CONSTANT THROUGHPUT
DELAY VALUE
TABLE 3 INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
TABLE 1 VARIABLE THROUGHPUT
DELAY VALUE
NOTE:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
TABLE 4 OUTPUT HIGH IMPEDANCE CONTROL
Delay for Variable Throughput Delay Mode
Input Rate (m – output channel number)
(n – input channel number)
m < n m = n, n+1, n+2 m > n+2
2.048 Mb/s 32 – (n-m) time-slots m-n + 32 time-slots m-n time-slots
Delay for Constant Throughput Delay Mode
Input Rate (m – output channel number)
(n – input channel number)
2.048 Mb/s 32 + (32 – n) + m time-slots
A7
(1)
A6 A5 A4 A3 A2 A1 A0 Location
00000000 Control Register, CR
00000001 Interface Mode Selection Register, IMS
00000010 Frame Alignment Register, FAR
00000011 Frame Input Offset Register 0, FOR0
00000100 Frame Input Offset Register 1, FOR1
00000101 Frame Input Offset Register 2, FOR2
00000110 Frame Input Offset Register 3, FOR3
10000000 Ch0
10000001 Ch1
100..... .
10011110 Ch30
10011111 Ch31
OE bit in Connection ODE pin OSB bit in IMS TX Output Driver
Memory Register Status
0 Don’t Care Don’t Care Per Channel
High-Impedance
1 0 0 High-Impedance
1 0 1 Enable
1 1 1 Enable
1 1 0 Enable

72V70200PFG8

Mfr. #:
Manufacturer:
IDT
Description:
Digital Bus Switch ICs 3.3V 512X512 TIS SWITCH
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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