72V70200PFG8 Datasheet 72V70200PFG8, 72V70200PF, 72V70200PF8 | P4-P6

COMMERCIAL TEMPERATURE RANGE

IDT72V70200 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 512 x 5

PIN DESCRIPTION

SYMBOL NAME I/O DESCRIPTION

GND Ground. Ground Rail.

Vcc Vcc +3.3 Volt Power Supply.

TX0-15

(1)

TX Output 0 to 15 O Serial data output stream. These streams have a data rate of 2.048 Mb/s.

(Three-state Outputs)

RX0-15

(1)

RX Input 0 to 15 I Serial data input stream. These streams have a data rate of 2.048 Mb/s.

F0i

(1)

Frame Pulse I This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS

and GCI specifications.

(1)

Frame Evaluation I This pin is the frame measurement input.

CLK

(1)

Clock I Serial clock for shifting data in/out on the serial streams (RX/TX 0-15). This input accepts a 4.096 MHz clock.

TMS Test Mode Select I JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-

up when not driven.

TDI Test Serial Data In I JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up

when not driven.

TDO Test Serial Data Out O JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when

JTAG scan is not enabled.

TCK

(1)

Test Clock I Provides the clock to the JTAG test logic.

TRST Test Reset I Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled

by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure

that the IDT72V70200 is in the normal functional mode.

(1)

Internal Connection I Connect to GND for normal operation. This pin must be LOW for the IDT72V70200 to function normally and to

comply with IEEE 1114 (JTAG) boundary scan requirements.

RESET

(1)

Device Reset I This input (active LOW) puts the IDT72V70200 in its reset state that clears the device internal counters, registers

(Schmitt Trigger Input) and brings TX0-15 and microport data outputs to a high-impedance state. The time constant for a power up

reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET

pin must be held LOW for a minimum of 100ns to reset the device.

A0-7

(1)

Address 0-7 I When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal

memories.

DS/RD

(1)

Data Strobe/Read I For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with

CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS.

This active LOW input works in conjunction with CS to enable the read and write operations. For Intel multiplexed

bus operation, this input is RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.

R/W / WR

(1)

Read/Write / Write I In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls

the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus

operation, this input is WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs.

(1)

Chip Select I Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70200.

AS/ALE

(1)

Address Strobe or I This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed

Latch Enable bus operation, connect this pin to ground.

(1)

CPU Interface Mode I When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor

port is in non-multiplexed mode.

AD0-7

(1)

Address/Data Bus 0 to 7 I/O These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins

are also the input address bits of the microprocessor port.

D8-15

(1)

Data Bus 8-15 I/O These pins are the eight most significant data bits of the microprocessor port.

DTA

(1)

Data Transfer O This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin

Acknowledgment drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A

pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.

CCO

(1)

Control Output O This is a 4.096 Mb/s output containing 512 bits per frame respectively. The level of each bit is determined by

the CCO bit in the connection memory. See External Drive Control Section.

ODE

(1)

Output Drive Enable I This is the output enable control for the TX0 to TX15 serial outputs. When ODE input is LOW and the OSB

bit of the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15

output drivers are enabled. However, each channel may still be put into a high-impedance state by using the

per channel control bit in the connection memory.

NOTE:

1. These pins are 5V tolerant.

COMMERCIAL TEMPERATURE RANGE

IDT72V70200 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 512 x 5

FUNCTIONAL DESCRIPTION

The IDT72V70200 is capable of switching 512 x 512, 64 Kbit/s PCM or

N x 64 Kbit/s channel data. The device maintains frame integrity in data

applications and minimum throughput delay for voice applications on a per

channel basis.

The serial input streams of the IDT72V70200 can have a bit rate of

2.048 Mb/s and are arranged in 125μs wide frames, which contain 32 channels

respectively. The data rates on input and output streams are identical.

In Processor Mode, the microprocessor can access input and output time-

slots on a per channel basis allowing for transfer of control and status information.

The IDT72V70200 automatically identifies the polarity of the frame synchroni-

zation input signal and configures the serial streams to either ST-BUS

or GCI

formats.

With the variety of different microprocessor interfaces, IDT72V70200 has

provided an Input Mode pin (IM) to help integrate the device into different

microprocessor based environments: Non-multiplexed or Multiplexed. These

interfaces provide compatibility with multiplexed and Motorola non-multiplexed

buses. The device can also resolve different control signals eliminating the use

of glue logic necessary to convert the signals (R/W/WR, DS/RD, AS/ALE).

The frame offset calibration function allows users to measure the frame offset

delay using a frame evaluation pin (FE). The input offset delay can be

programmed for individual streams using internal frame input offset registers, see

Table 8.

The internal loopback allows the TX output data to be looped around to the

RX inputs for diagnostic purposes.

A functional Block Diagram of the IDT72V70200 is shown in Figure 1.

DATA AND CONNECTION MEMORY

The received serial data is converted to parallel format by internal serial-

to-parallel converters and stored sequentially in the data memory. The 8KHz

input frame pulse (F0i) is used to generate channel and frame boundaries of

the input serial data. Depending on the interface mode select (IMS) register,

the usable data memory may be as large as 512 bytes.

Data to be output on the serial streams (TX0-15) may come from either the

data memory or connection memory. For data output from data memory

(connection mode), addresses in the connection memory are used. For data

to be output from connection memory, the connection memory control bits must

set the particular TX output in Processor Mode. One time-slot before the data

is to be output, data from either connection memory or data memory is read

internally. This allows enough time for memory access and parallel-to-serial

conversion.

CONNECTION AND PROCESSOR MODES

In the Connection Mode, the addresses of the input source data for all output

channels are stored in the connection memory. The connection memory is

mapped in such a way that each location corresponds to an output channel on

the output streams. For details on the use of the source address data (CAB and

SAB bits), see Table 10. Once the source address bits are programmed by the

microprocessor, the contents of the data memory at the selected address are

transferred to the parallel-to-serial converters and then onto a TX output stream.

By having the each location in the connection memory specify an input

channel, multiple outputs can specify the same input address. This can be a

powerful tool used for broadcasting data.

In Processor Mode, the microprocessor writes data to the connection

memory. Each location in the connection memory corresponds to a particular

output stream and channel number and is transferred directly to the parallel-to-

serial converter one time-slot before it is to be output. This data will be output

on the TX streams in every frame until the data is changed by the microprocessor.

As the IDT72V70200 can be used in a wide variety of applications, the device

also has memory locations to control the outputs based on operating mode.

Specifically, the IDT72V70200 provides five per-channel control bits for the

following functions: processor or connection mode, constant or variable delay,

enables/three-state the TX output drivers and enables/disable the loopback

function. In addition, one of these bits allows the user to control the CCO output.

If an output channel is set to a high-impedance state through the connection

memory, the TX output will be in a high-impedance state for the duration of that

channel. In addition to the per-channel control, all channels on the ST-BUS

outputs can be placed in a high impedance state by either pulling the ODE input

pin low or programming the Output Stand-By (OSB) bit in the interface mode

selection register. This action overrides the per-channel programming in the

connection memory bits.

The connection memory data can be accessed via the microprocessor

interface. The addressing of the devices internal registers, data and connection

memories is performed through the address input pins and the Memory Select

(MS) bit of the control register. For details on device addressing, see Software

Control and Control Register bits description (Table 3 and 5).

SERIAL DATA INTERFACE TIMING

The master clock frequency must always be twice the data rate. For serial

data rates of 2.048 Mb/s, the master clock (CLK) must be at 4.096 MHz. The

input and output stream data rates will always be identical.

The input 8 KHz frame pulse can be in either ST-BUS

or GCI format. The

IDT72V70200 automatically detects the presence of an input frame pulse and

identifies it as either ST-BUS

or GCI. In ST-BUS

format, every second falling

edge of the master clock marks a bit boundary and the data is clocked in on the

rising edge of CLK, three quarters of the way into the bit cell, see Figure 7. In

GCI format, every second rising edge of the master clock marks the bit boundary

and data is clocked in on the falling edge of CLK at three quarters of the way

into the bit cell, see Figure 8.

INPUT FRAME OFFSET SELECTION

Input frame offset selection allows the channel alignment of individual input

streams to be offset with respect to the output stream channel alignment (i.e. F0i).

Although all input data comes in at the same speed, delays can be caused by

variable path serial backplanes and variable path lengths which may be

implemented in large centralized and distributed switching systems. Because

data is often delayed, this feature is useful in compensating for the skew between

clocks.

Each input stream can have its own delay offset value by programming the

frame input offset registers (FOR). The maximum allowable skew is +4.5 master

clock (CLK) periods forward with resolution of ½ clock period. The output frame

offset cannot be offset or adjusted. See Figure 5, Table 8 and 9 for delay offset

programming.

SERIAL INPUT FRAME ALIGNMENT EVALUATION

The IDT72V70200 provides the frame evaluation (FE) input to determine

different data input delays with respect to the frame pulse F0i.

A measurement cycle is started by setting the start frame evaluation (SFE)

bit low for at least one frame. When the SFE bit in the IMS register is changed

from low to high, the evaluation starts. Two frames later, the complete frame

evaluation (CFE) bit of the frame alignment register (FAR) changes from low

to high to signal that a valid offset measurement is ready to be read from bits 0

COMMERCIAL TEMPERATURE RANGE

IDT72V70200 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 512 x 5

to 11 of the FAR register. The SFE bit must be set to zero before a new

measurement cycle started.

In ST-BUS

mode, the falling edge of the frame measurement signal (FE)

is evaluated against the falling edge of the ST-BUS

frame pulse. In GCI mode,

the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.

See Table 7 and Figure 4 for the description of the frame alignment register.

MEMORY BLOCK PROGRAMMING

The IDT72V70200 provides users with the capability of initializing the entire

connection memory block in two frames. To set bits 11 to 15 of every connection

memory location, first program the desired pattern in bits 5 to 9 of the IMS register.

The block programming mode is enabled by setting the memory block

program (MBP) bit of the control register high. When the block programming

enable (BPE) bit of the IMS register is set to high, the block programming data

will be loaded into the bits 11 to 15 of every connection memory location. The

other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the

memory block programming is complete, the device resets the BPE bit to zero.

LOOPBACK CONTROL

The loopback control (LPBK) bit of each connection memory location allows

the TX output data to be looped backed internally to the RX input for diagnostic

purposes.

If the LPBK bit is high, the associated TX output channel data is internally

looped back to the RX input channel (i.e., data from TX n channel m routes to

the RX n channel m internally); if the LPBK bit is low, the loopback feature is

disabled. For proper per-channel loopback operation, the contents of frame

delay offset registers must be set to zero.

DELAY THROUGH THE IDT72V70200

The switching of information from the input serial streams to the output serial

streams results in a throughput delay. The device can be programmed to

perform time-slot interchange functions with different throughput delay capabili-

ties on the per-channel basis. For voice applications, variable throughput delay

is best as it ensures minimum delay between input and output data. In wideband

data applications, constant throughput delay is best as the frame integrity of the

information is maintained through the switch.

The delay through the device varies according to the type of throughput

delay selected in the V/C bit of the connection memory.

VARIABLE DELAY MODE (V/C BIT = 0)

In this mode, the delay is dependent only on the combination of source and

destination channels and is independent of input and output streams. The

minimum delay achievable in the IDT72V70200 is three time-slots. If the input

channel data is switched to the same output channel (channel n, frame p), it will

be output in the following frame (channel n, frame p+1). The same is true if input

channel n is switched to output channel n+1 or n+2. If the input channel n is

switched to output channel n+3, n+4,..., the new output data will appear in the

same frame. Table 1 shows the possible delays for the IDT72V70200 in the

variable delay mode.

CONSTANT DELAY MODE (V/C BIT = 1)

In this mode, frame integrity is maintained in all switching configurations by

making use of a multiple data memory buffer. Input channel data is written into

the data memory buffers during frame n will be read out during frame n+2. In

the IDT72V70200, the minimum throughput delay achievable in the constant

delay mode will be one frame. For example, when input time-slot 31 is switched

to output time-slot 0. The maximum delay of 94 time-slots of delay occurs when

time-slot 0 in a frame is switched to time-slot 31 in the frame. See Table 2.

MICROPROCESSOR INTERFACE

The IDT72V70200 provides a parallel microprocessor interface for multi-

plexed or non-multiplexed bus structures. This interface is compatible with

Motorola non-multiplexed and multiplexed buses.

If the IM pin is low a Motorola non-multiplexed bus should be connected to

the device. If the IM pin is high, the device monitors the AS/ALE and DS/RD to

determine what mode the IDT72V70200 should operate in.

If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed

timing is selected. If DS/RD is high at the rising edge of AS/ALE, then the mode

2 multiplexed bus timing is selected.

For multiplexed operation, the required signals are the 8-bit data and

address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch

enable (AS/ ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR),

Chip select (CS) and Data transfer acknowledge (DTA). See Figure 11 and

Figure 12 for multiplexed parallel microport timing.

For the Motorola non-multiplexed bus, the required signals are the 16-bit

data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines

(CS, DS, R/W and DTA). See Figure 13 and 14 for Motorola non-multiplexed

microport timing.

The IDT72V70200 microport provides access to the internal registers,

connection and data memories. All locations provide read/write access except

for the data memory and the frame alignment register which are read only.

MEMORY MAPPING

The address bus on the microprocessor interface selects the internal

registers and memories of the IDT72V70200.

If the A7 address input is low, then A6 through A0 are used to address the

interface mode selection (IMS), control (CR), frame alignment (FAR) and frame

input offset (FOR) registers (Table 4). If the A7 is high, A6 and A5 are low, then

A4 through A0 are used to select 32 locations corresponding to data rate of the

ST-BUS

. The address input lines and the stream address bits (STA) of the

control register allow access to the entire data and connection memories. The

control and IMS registers together control all the major functions of the device,

see Figure 3.

As explained in the Serial Data Interface Timing and Switching Configura-

tions sections, after system power-up, the IMS register should be programmed

immediately to establish the desired switching configuration.

The data in the control register consists of the memory block programming

bit (MBP), the memory select bit (MS) and the stream address bits (STA). As

explained in the Memory Block Programming section, the MBP bit allows the

entire connection memory block to be programmed. The memory select bit is

used to designate the connection memory or the data Memory. The stream

address bits select internal memory subsections corresponding to input or output

serial streams.

The data in the IMS register consists of block programming bits (BPD0-

BPD4), block programming enable bit (BPE), output stand by bit (OSB) and start

frame evaluation bit (SFE). The block programming and the block programming

enable bits allows users to program the entire connection memory (see Memory

Block Programming section). If the ODE pin is low, the OSB bit enables (if high)

or disables (if low) all ST-BUS

output drivers. If the ODE pin is high, the contents

of the OSB bit is ignored and all TX output drivers are enabled.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

72V70200PFG8

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