LTC2488
13
2488fb
For more information www.linear.com/LTC2488
APPLICATIONS INFORMATION
pin on the falling edge of SCK and data is shifted into the
SDI pin on the rising edge of SCK.
The serial clock pin (SCK) can be configured as either a
master (SCK is an output generated internally) or a slave
(SCK is an input and applied externally). Master mode
(Internal SCK) is selected by simply floating the SCK pin.
Slave mode (External SCK) is selected by driving SCK low
during power up and each falling edge of CS. Specific
details of these SCK modes are described in the Serial
Interface Timing Modes section.
Serial Data Output (SDO)
The serial data output pin (SDO) provides the result of the
last conversion as a serial bit stream (MSB first) during
the data output state. In addition, the SDO pin is used as
an end of conversion indicator during the conversion and
sleep states.
When CS is HIGH, the SDO driver is switched to a high
impedance state in order to share the data output line with
other devices. If CS is brought LOW during the conversion
phase, the EOC bit (SDO pin) will be driven HIGH. Once
the conversion is complete, if CS is brought LOW, EOC
will
be driven LOW indicating the conversion is complete
and the result is ready to be shifted out of the device.
Chip Select (CS)
The active low CS pin is used to test the conversion status,
enable I/O data transfer, initiate a new conversion, control
the duration of the sleep state, and set the SCK mode.
At the conclusion of a conversion cycle, while CS is HIGH,
the device remains in a low power sleep state where the
supply current is reduced several orders of magnitude. In
order to exit the sleep state and enter the data output state,
CS must be pulled low. Data is now shifted out the SDO
pin under control of the SCK pin as described previously.
A new conversion cycle is initiated either at the conclusion
of the data output cycle (all 24 data bits read) or by pulling
CS HIGH any time between the first and 24th rising edges
of the serial clock (SCK). In this case, the data output is
aborted and a new conversion begins.
Serial Data Input (SDI)
The serial data input (SDI) is used to select the input chan
-
nel. Data is shifted into the device during the data output/
input state on the rising edge of SCK while CS is low.
OUTPUT DATA FORMAT
The LTC2488 serial output stream is 24 bits long. The
first bit indicates the conversion status, the second bit is
always zero, and the third bit conveys sign information.
The next 17 bits are the conversion result, MSB first. The
remaining 4 bits are always LOW.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available on the SDO pin during the
conversion and sleep states whenever CS is LOW. This bit
is HIGH during the conversion cycle, goes LOW once the
conversion is complete, and is HIGH-Z when CS is HIGH.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign indicator
(SIG). If the selected input (V
IN
= IN
+
– IN
–
) is greater than
or equal to 0V, this bit is HIGH. If V
IN
< 0, this bit is LOW.
Bit 20 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 21 also pro
-
vides underrange and overrange indication. If both Bit 21
and Bit 20 are HIGH, the differential input voltage is above
+FS. If both Bit 21 and Bit 20 are LOW, the differential
input
voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2488 Status Bits
Input Range Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
MSB
V
IN
≥ 0.5 • V
REF
0 0 1 1
0V ≤ V
IN
< 0.5 • V
REF
0 0 1 0
–0.5 • V
REF
≤ V
IN
< 0V 0 0 0 1
V
IN
< –0.5 • V
REF
0 0 0 0
Bits 20 to 4 are the 16-bit plus sign conversion result
MSB first.
Bit 4 is the least significant bit (LSB
16
).
Bits 3 to 0 are always LOW.
