LTC2488
18
2488fb
For more information www.linear.com/LTC2488
APPLICATIONS INFORMATION
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 7).
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating or pulled HIGH
before the conclusion of the POR cycle and prior to each
falling edge of CS. An internal weak pull-up resistor is active
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while the conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit sleep state. In order to return to the
sleep state and reduce the power
consumption, CS
must be
pulled HIGH before the device pulls SCK HIGH. When the
device is using its own internal oscillator (F
O
is tied LOW),
the first rising edge of SCK occurs 12µs (t
EOCTEST
= 12µs)
after the falling edge of CS. If F
O
is driven by an external
oscillator of frequency f
EOSC
, then t
EOCTEST
= 3.6/f
EOSC
.
If CS remains LOW longer than t
EOCTEST
, the first rising
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
After the 24th rising edge of SCK a new conversion au
-
tomatically begins. SDO goes HIGH (EOC = 1) and SCK
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH any time between the 1st rising edge and the 24th
falling edge of SCK (see Figure 8). On the rising edge of
CS, the device aborts the data output state and immediately
initiates a new conversion. In order
to program a new
input
channel, 8 SCK clock pulses are required. If the data
output sequence is aborted prior to the 8th falling edge
V
CC
F
O
SCK
SDI
GND
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2488
3-WIRE
SPI INTERFACE
REF
+
REF
–
CH0
CH1
CH2
CH3
COM
SDO
12 1
13
14
8
9
10
11
7
3
5
6
4
2
2.7V TO 5.5V
0.1µF
10µF
CS
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2488 F06
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
1 0 EN SGL A2 A1 A0ODD
BIT 0
DON'T CAREDON'T CARE
MSBSIG“0”
1 2 3 4 5 6 7 8 9 19 20 21 22 23 24
LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Figure 6. External Serial Clock, 3-Wire Operation (CS = 0)
