FEATURES
Single Power Supply Operation
- Low voltage range: 2.70 V - 3.60 V
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- IS39LV040: 512K x 8 (4 Mbit)
- IS39LV010: 128K x 8 (1 Mbit)
- IS39LV512: 64K x 8 (512 Kbit)
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- 70 ns access time
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- Uniform 4 Kbyte sectors
- Uniform 64 Kbyte blocks (sector group - except
IS39LV512)
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- Typical 16 μs/byte programming time
- Typical 55 ms sector/block/chip erase time
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- Typical 4 mA active read current
- Typical 8 mA program/erase current
- Typical 0.1 μA CMOS standby current
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- 100,000 program/erase cycles per single sector
- Minimum 20 years data retention
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- 32-pin (8 mm x 14 mm) VSOP
- 32-pin PLCC
- Optional lead-free (Pb-free) package
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- IS39LV040/010/512 0
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The IS39LV040/010/512 are 4 Mbit / 1 Mbit / 512 Kbit 3.0 Volt-only Flash Memories. These devices are designed
to use a single low voltage, range from 2.70 Volt to 3.60 Volt, power supply to perform read, erase and program
operations. The 12.0 Volt V
PP
power supply for program and erase operations are not required. The devices can
be programmed in standard EPROM programmers as well.
The memory array of IS39LV512 is divided into uniform 4 Kbyte sectors for data or code storage. The memory
arrays of IS39LV010/040 are divided into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks (sector group -
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area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting the data in
others. The chip erase feature allows the whole memory array to be erased in one single erase operation. The
devices can be programmed on a byte-by-byte basis after performing the erase operation.
The devices have a standard microprocessor interface as well as a JEDEC standard pin-out/command set. The
program operation is executed by issuing the program command code into command register. The internal control
logic automatically handles the programming voltage ramp-up and timing. The erase operation is executed by
issuing the chip erase, block, or sector erase command code into command register. The internal control logic
automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not
been programmed is not required before an erase operation. The devices offer Data# Polling and Toggle Bit
functions, the progress or completion of program and erase operations can be detected by reading the Data#
Polling on I/O7 or the Toggle Bit on I/O6.
The IS39LV040/010/512 are manufactured on pFLASH™’s advanced nonvolatile CMOS technology. The devices
are offered in 32-pin VSOP and PLCC packages with 70 ns access time.
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Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. B
07/29/2015
