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Integrated Silicon Solution, Inc. — www.issi.com 5
Rev. B
07/29/2015
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The entire memory array can be erased through a chip
erase operation. Pre-programs the devices are not
required prior to a chip erase operation. Chip erase
starts immediately after a six-bus-cycle chip erase
command sequence. All commands will be ignored
once the chip erase operation has started. The devices
will return to standby mode after the completion of chip
erase.
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The memory array of IS39LV040/010/512 are organized
into uniform 4 Kbyte sectors. A sector erase operation
allows to erase any individual sector without affecting
the data in others. The memory array of IS39LV010/040,
excluding IS39LV512, are also organized into uniform
64 Kbyte blocks (sector group - consists of sixteen
adjacent sectors). A block erase operation allows to
erase any individual block. The sector or block erase
operation is similar to chip erase.
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The IS39LV040/010/512 provide a Data# Polling fea-
ture to indicate the progress or completion of a program
and erase cycles. During a program cycle, an attempt
to read the devices will result in the complement of the
last loaded data on I/O7. Once the program operation
is completed, the true data of the last loaded data is
valid on all outputs. During a sector, block, or chip erase
cycle, an attempt to read the device will result a “0” on
I/O7. After the erase operation is completed, an attempt
to read the device will result a “1” on I/O7.
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The IS39LV040/010/512 also provide a Toggle Bit fea-
ture to detect the progress or completion of a program
and erase cycles. During a program or erase cycle, an
attempt to read data from the device will result a tog-
gling between “1” and “0” on I/O6. When the program
or erase operation is complete, I/O6 will stop toggling
and valid data will be read. Toggle bit may be accessed
at any time during a program or erase cycle.
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Hardware data protection protects the devices from un-
intentional erase or program operation. It is performed
in the following ways: (a) V
CC
sense: if V
CC
is below 1.8
V (typical), the write operation is inhibited. (b) Write
inhibit: holding any of the signal OE# low, CE# high, or
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of less than 5 ns (typical) on the WE# or CE# input will
not initiate a write operation.
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Manufacturer ID 9Dh
Device ID:
IS39LV040 3Eh
IS39LV010 1Ch
IS39LV512 1Bh
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