Data Sheet ADMV1009
Rev. B | Page 19 of 23
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
The typical applications circuit is shown in Figure 59. The
application circuit shown has been replicated for the evaluation
board circuit.
U1
ADMV1009AEZ
C12
100pF
C13
10nF
C14
1µF
C3
1µF
C2
10nF
C1
100pF
24
NIC
23
NIC
22
NIC
21
NIC
20
NIC
19
LOIN
LOIN
18
GND
17
NIC
1
2
3
4
5
6
7
8
NIC
GND
RFOUT
RFOUT
J1
SMA
SMA
SMA
SMA
J2
J3
NIC
NIC
NIC
VGRF
VGRF
TP5
TP1
VDRF
NIC
L1
56nH
L2
56nH
SEC_DOT
GND
NC
NC
4
5
6
SEC_BAL
3300MHz TO 4000MHz
NCS1-422+
U2
PRI_GND
PRI_DOT
IFIN
3
2
1
C15
10pF
C16
10pF
9
10
11
12
13
14
15
16
NIC
GND
IF2
NIC
NIC
IF1
GND
NIC
32
31
30
29
28
27
26
25
NIC
VDRF
NIC
VGMX
NIC
VDLO
VGLO
NIC
C5
1µF
C4
100pF
TP2
VGX
C8
1µF
C7
10nF
C6
470pF
TP3
VDLO
C11
1µF
C10
10nF
C9
100pF
TP4
5016
5016
5016
5016
VGLO
TP6
5016
5016
15770-059
Figure 59. Typical Application Circuit
ADMV1009 Data Sheet
Rev. B | Page 20 of 23
EVALUATION BOARD INFORMATION
The circuit board used in the application must use RF circuit
design techniques. Signal lines must have 50 Ω impedance, and
the package ground leads and exposed pad must be connected
directly to the ground plane, similar to what is shown in Figure 60
and Figure 61. Use a sufficient number of via holes to connect
the top and bottom ground planes. The evaluation circuit board
shown in Figure 59 is available from Analog Devices, Inc., upon
request.
Layout
Solder the exposed pad on the underside of the ADMV1009 to
a low thermal and electrical impedance ground plane. This pad
is typically soldered to an exposed opening in the solder mask
on the evaluation board. Connect these ground vias to all other
ground layers on the evaluation board to maximize heat
dissipation from the device package. Figure 60 shows the PCB
land pattern footprint for the ADMV1009-EVALZ, and Figure 61
shows the solder paste stencil for the ADMV1009-EVALZ
evaluation board.
Power-On Sequence
To set up the ADMV1009-EVALZ , take the following steps:
1. Power up the VGLO with a 1.5 V supply.
2. Power up the VDLO with a 5 V supply.
3. Adjust VGLO from −1.5 V to 0.5 V such that IDLO =
60 mA.
4. Power up VGRF with a 1.5 V supply.
5. Power up VDRF with a 5 V supply.
6. Adjust VGRF from 1.5 V to 0.5 V such that IDLO =
250 mA
7. Power up VGMIX with a 1.5 V supply.
8. Apply an LO signal.
9. Apply an IF signal.
Power Off Sequence
To tur n off the ADMV1009-EVA L Z , take the following steps:
1. Turn off the LO and IF signals.
2. Set VGRF and VGLO to 1.5 V.
3. Set the VDRF and VDLO supplies to 0 V and then turn off
the VDRF and VDLO supplies.
4. Turn off the VGRF and VGLO supplies.
0.138" SQUARE MASK OPENING
0.02 × 45° CHAMFER FOR PIN 1
0.197"
[0.50]
PAD SIZE
0.026" × 0.010"
0.217" SQUARE
0.004" MASK/METAL OVERLAP
0.010" MINIMUM MASK WIDTH
0.010" REF
0.030"
MASK OPENING
0.156"
MASK
OPENING
PIN 1
GROUND PAD
SOLDER MASK
0.146" SQUARE
GROUND PAD
ø.010"
TYPICAL VIA
ø.034"
TYPICAL
VIA SPACING
15770-104
Figure 60. PCB Land Pattern Footprint of the ADMV1009-EVALZ
Data Sheet ADMV1009
Rev. B | Page 21 of 23
0.219
SQUARE
0.017
0.017
0.027
TYP
0.010
TYP
0.0197
TYP
R0.0040 TYP
132 PLCS
0.132
SQUARE
15770-105
Figure 61. Solder Paste Stencil of the ADMV1009-EVALZ
15770-062
Figure 62. ADMV1009-EVALZ Evaluation Board Top Layer

ADMV1009AEZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Up-Down Converters 13/15GHz GaAs UpConverter
Lifecycle:
New from this manufacturer.
Delivery:
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