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ADMV1012AEZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
17.5 GHz to 24 GHz,
GaAs, MMIC, I/Q Downconverter
Data Sheet
ADMV1012
Rev. A Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2017–2018 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
RF input frequency range: 17.5 GHz to 24 GHz
IF output frequency range: 2.5 GHz to 3.5 GHz
LO input frequency range: 7 GHz to 13.5 GHz
Conversion gain (with hybrid): 15 dB typical
SSB noise figure: 2.5 dB typical
Input IP3: 3 dBm typical
Input P1dB: −5 dBm typical
25 dB of image rejection
Single-ended, 50 Ω RF and LO input ports
Exposed pad, 4.9 mm × 4.9 mm, 32-terminal LCC
APPLICATIONS
Point to point microwave radios
Radars and electronic warfare systems
Instrumentation, automatic test equipment (ATE)
Satellite communications
FUNCTIONAL BLOCK DIAGRAM
31
20
10
3
15
22
27
×2
IF2
LOIN
RFIN
VDRF VGRF
VDLO
IF1
ADMV1012
16349-001
2
4
GND
GND
11
GND
Figure 1.
GENERAL DESCRIPTION
The ADMV1012 is a compact, gallium arsenide (GaAs)
design, monolithic microwave integrated circuit (MMIC), in
phase/quadrature (I/Q) downconverter in a RoHS compliant
package optimized for point to point microwave radio designs
that operate in the 17.5 GHz to 24 GHz input frequency range.
The ADMV1012 provides 15 dB of conversion gain with 25 dB
of image rejection, and 2.5 dB noise figure. The ADMV1012
uses a radio frequency (RF) low noise amplifier (LNA) followed
by an I/Q, double balanced mixer, where a driver amplifier drives
the local oscillator (LO) with a ×2 multiplier. IF1 and IF2 mixer
quadrature outputs are provided, and an external 90° hybrid is
required to select the required sideband.
The I/Q mixer topology reduces the need for filtering of unwanted
sideband. The ADMV1012 is a much smaller alternative to
hybrid style, double sideband (DSB) downconverter assemblies
and eliminates the need for wire bonding by allowing the use of
surface-mount manufacturing assemblies.
The ADMV1012 downconverter comes in a compact, thermally
enhanced, 4.9 mm × 4.9 mm, 32-terminal LCC. The ADMV1012
operates over the −40°C to +85°C temperature range.
ADMV1012 Data Sheet
Rev. A | Page 2 of 19
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 6
Upper Sideband (Low-Side LO) ................................................. 6
Lower Sideband (High-Side LO) ................................................ 8
IF Bandwidth .............................................................................. 10
Leakage Performance ................................................................. 11
Return Loss Performance .......................................................... 12
Spurious Performance ............................................................... 13
M × N Spurious Performance for LO = 0 dBm ...................... 13
Theory of Operation ...................................................................... 14
LO Driver Amplifier .................................................................. 14
Mixer ............................................................................................ 14
LNA .............................................................................................. 14
Applications Information .............................................................. 15
Typical Application Circuit ....................................................... 15
Evaluation Board Information ................................................. 16
Bill of Materials ........................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
2/2018—Rev. 0 to Rev. A
Changes to Features Section, General Description Section, and
Figure 1 .............................................................................................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Added Thermal Resistance Section and Table 3; Renumbered
Sequentially ....................................................................................... 4
Changes to Figure 2 and Table 4 ..................................................... 5
Changes to Figure 3 and Figure 6 ................................................... 6
Changes to Figure 12 ........................................................................ 7
Changes to Figure 24, Figure 25, and Figure 26 ......................... 10
Changes to Figure 27 through Figure 30 ..................................... 11
Changed M × N Spurious Performance for LO = 4 dBm Section
to M × N Spurious Performance for LO = 0 dBm Section ....... 13
Changes to M × N Spurious Performance for LO = 0 dBm
Sec tion .............................................................................................. 13
Changes to LO Driver Amplifier Section .................................... 14
Changes to Applications Information Section and Figure 34 ........ 15
Changes to Power-On Sequence Section .................................... 16
Changes to Figure 37 ...................................................................... 17
Changes to Table 6 .......................................................................... 18
Changes to Ordering Guide .......................................................... 19
10/2017—Revision 0: Initial Version
Data Sheet ADMV1012
Rev. A | Page 3 of 19
SPECIFICATIONS
Data taken at VDRF = 3 V, V D L O = 3 V, LO = −4 dBm ≤ LO ≤ +4 dBm, −40°C ≤ T
A
≤ +85°C, with a Mini-Circuits® QCN-45+ power
splitter for both upper sideband (low-side LO) and lower sideband (high-side LO), unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT FREQUENCY RANGE
Radio Frequency RF 17.5 24 GHz
Local Oscillator LO 7 13.5 GHz
LO AMPLITUDE −4 0 +4 dBm
OUTPUT FREQUENCY RANGE
Intermediate Frequency IF 2.5 3.5 GHz
RF PERFORMANCE With hybrid
Conversion Gain 10.5 15 20 dB
Single Sideband (SSB) Noise Figure
SSB NF
Lower Sideband (High-Side LO) 2.1 3.5 dB
Upper Sideband (Low-Side LO) 2.5 4 dB
Input Third-Order Intercept IP3 At −20 dBm/tone 0 3 dBm
Input 1 dB Compression Point P1dB −9 −5 dBm
Image Rejection 20 25 dB
Leakage
LO to RF −37 −25 dBm
LO to IF −40 −25 dBm
2× LO to IF −40 −25 dBm
IM3 at Input
−20 dBm Input Power −23 dBm per tone 46 52 dBc
−25 dBm Input Power −28 dBm per tone 52 60 dBc
−30 dBm Input Power −33 dBm per tone 56 70 dBc
Return Loss
RF Input −11 −10 dB
IF Output −23 −10 dB
LO Input
−11
−10
dB
POWER INTERFACE
RF LNA Bias Voltage VDRF 3 3.5 V
LO Amplifier Bias Voltage VDLO 3 3.5 V
RF LNA Gate Voltage VGRF −1.8 −0.4
RF Amplifier Bias Current IDRF Adjust VGRF between −1.8 V to −0.4 V to get IDRF 68 mA
LO Amplifier Bias Current IDLO 170 mA
RF Amplifier Gate Current IGRF <1 mA
Total Power 0.7 0.8 W
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

ADMV1012AEZ

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Up-Down Converters 18/23GHz GaAs D/C
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