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MPC9443AER2

P1-P3P4-P6P7-P9P10-P12P13-P15
MPC9443
REVISION 6 3/14/16 10 ©2016 Integrated Device Technology, Inc.
MPC9443 Data Sheet 2.5V, 3.3V LVCMOS CLOCK FANOUT BUFFER
Figure 6. Maximum MPC9443 frequency, V
CC
= 3.3 V,
MTBF 9.1 Years, Driving Series Terminated
Transmission Lines
Figure 7. Maximum MPC9443 Frequency, V
CC
= 3.3 V, MTBF
9.1 Years, 4 pF Load per Line
Figure 8. Maximum MPC9443 Frequency, V
CC
= 3.3 V,
MTBF 4 Years, Driving Series Terminated
Transmission Lines
Figure 9. Maximum MPC9443 Frequency, V
CC
= 3.3 V, MTBF
4 Years, 4 pF Load per Line
MPC9443
REVISION 6 3/14/16 11 ©2016 Integrated Device Technology, Inc.
MPC9443 Data Sheet 2.5V, 3.3V LVCMOS CLOCK FANOUT BUFFER
Figure 10. CCLK MPC9443 AC Test Reference for V
cc
= 3.3 V and V
cc
= 2.5 V
Figure 11. PCLK MPC9443 AC Test Reference
Figure 12. Propagation Delay (t
PD
) Test Reference
Figure 13. Propagation Delay (t
PD
) Test Reference
Figure 14. Output-to-Output Skew t
SK(LH, HL)
Figure 15. Output Pulse Skew (t
SK(P)
) Test Reference
Pulse
Generator
Z = 50
R
T
= 50
Z
O
= 50
R
T
= 50
Z
O
= 50
MPC9443 DUT
V
TT
V
TT
V
CC
GND
PCLK
Q
X
PCLK
V
PP
t
P(LH)
t
P(HL)
V
CMR
V
CC
2
V
CC
V
CC
2
GND
V
CC
V
CC
2
GND
CCLK
Q
X
t
P(LH)
t
P(HL)
The pin-to-pin skew is defined as the worst case differ-
ence in propagation delay between any similar delay
path within a single device
V
CC
V
CC
2
GND
V
CC
V
CC
2
GND
t
SK(LH)
t
SK(HL)
V
CC
V
CC
2
GND
V
CC
V
CC
2
GND
t
P(LH)
CCLK
Q
X
t
P(HL)
t
SK(P)
= | t
PLH
– t
PHL
|
MPC9443
REVISION 6 3/14/16 12 ©2016 Integrated Device Technology, Inc.
MPC9443 Data Sheet 2.5V, 3.3V LVCMOS CLOCK FANOUT BUFFER
Figure 16. Output Duty Cycle (DC)
Figure 17. Output Transition Time Test Reference
Figure 18. Cycle-to-Cycle Jitter
Figure 19. Setup and Hold Time (t
S
, t
H
) Test Reference
The time from the PLL controlled edge to the non-controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
V
CC
V
CC
2
GND
t
P
T
0
DC = (t
P 
T
0
x 100%)
t
F
t
R
V
CC
= 3.3 V V
CC
= 2.5 V
2.4 1.8 V
0.55 0.6 V
The variation in cycle time of a signal between adjacent
cycles, over a random sample of adjacent cycle pairs
T
N
T
JIT(CC)
= |T
N
-T
N+1
|
T
N+1
V
CC
V
CC
2
GND
V
CC
V
CC
2
GND
t
S
CCLK
PCLK
CLK_STOP
t
H
P1-P3P4-P6P7-P9P10-P12P13-P15

MPC9443AER2

Mfr. #:
Buy MPC9443AER2
Manufacturer:
IDT
Description:
Clock Drivers & Distribution FSL 1-16 LVCMOS Fanout Buffer
Lifecycle:
New from this manufacturer.
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