MPC9443
REVISION 6 3/14/16 5 ©2016 Integrated Device Technology, Inc.
MPC9443 Data Sheet 2.5V, 3.3V LVCMOS CLOCK FANOUT BUFFER
Table 7. DC Characteristics (V
CC
= V
CCA
= V
CCB
= V
CCC
= V
CCD
= 3.3 V ± 5%, T
A
= –40 to +85°C)
Symbol Characteristics Min Typ Max Unit Condition
V
IH
Input High Voltage 2.0 V
CC
+ 0.3 V LVCMOS
V
IL
Input Low Voltage –0.3 0.8 V LVCMOS
V
PP
Peak-to-Peak Input Voltage PCLK0, 1 250 mV LVPECL
V
CMR
(1)
1. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range and the input
swing lies within the V
PP
(DC) specification.
Common Mode Range PCLK0, 1 1.1 V
CC
– 0.6 V LVPECL
I
IN
Input Current
(2)
2. Input pull-up / pull-down resistors influence input current.
200 A V
IN
= GND or V
IN
= V
CC
V
OH
Output High Voltage 2.4 V I
OH
= –24 mA
(3)
3. The MPC9443 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to
a termination voltage of V
TT
. Alternatively, the device drives up to two 50 series terminated transmission lines
(for V
CC
= 3.3 V) or one 50 series terminated transmission line (for V
CC
= 2.5 V).
V
OL
Output Low Voltage 0.55
0.30
V
V
I
OL
= 24 mA
(3)
I
OL
= 12 mA
Z
OUT
Output Impedance 19
I
CCQ
(4)
4. I
CCQ
is the DC current consumption of the device with all outputs open and the input in its default state or open.
Maximum Quiescent Supply Current 3.0 mA All V
CC
Pins
Table 8. AC Characteristics (V
CC
= V
CCA
= V
CCB
= V
CCC
= V
CCD
= 3.3 V ± 5%, T
A
= –40 to +85°C)
(1)
1. AC characteristics apply for parallel output termination of 50 to V
TT
.
Symbol Characteristics Min Typ Max Unit Condition
f
ref
Input Frequency 0 350 MHz
f
MAX
Maximum Output Frequency 1 output
2 output
0
0
350
175
MHz
MHz
FSELx = 0
FSELx = 1
V
PP
Peak-to-Peak Input Voltage PCLK0,1 500 1000 mV LVPECL
V
CMR
(2)
2. V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range and the input
swing lies within the V
PP
(AC) specification.
Common Mode Range PCLK0,1 1.3 V
CC
– 0.8 V LVPECL
t
P, REF
Reference Input Pulse Width 1.4 ns
t
r
, t
f
CCLK Input Rise/Fall Time 1.0
(3)
3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
ns 0.8 to 2.0 V
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay PCLK0,1 to any Q
PCLK0,1 to any Q
CCLK to any Q
CCLK to any Q
2.5
2.4
2.1
1.9
5.0
5.2
4.2
4.6
ns
ns
ns
ns
t
PLZ, HZ
Output Disable Time 10 ns
t
PZL, LZ
Output Enable Time 10 ns
t
S
, t
H
Setup, Hold Time (reference clock to CLK_STOP) 500 ps
t
sk(LH, HL)
Output-to-Output Skew
(4)
Within one bank
Any output, same output divider
Any output, any output divider
4. t
sk(LH, HL)
includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge.
125
225
250
ps
ps
ps
t
sk(PP)
Device-to-Device Skew (LH)
(5)
Using PCLK0,1
Using CCLK
Device-to-Device Skew (LH, HL)
(6)
Using PCLK0,1
Using CCLK
5. Device-to-device skew referenced to the rising output edge.
6. Device-to-device skew referenced to the rising output edge or referenced to the falling output edge.
2.5
2.1
2.8
2.7
ns
ns
ns
ns
t
SK(P)
DC
Q
Output Pulse Skew
(7)
Using PCLK0,1
Using CCLK
Output Duty Cycle f
Q
<140 MHz and using CCLK
f
Q
<250 MHz and using PCLK0,1
7. Output pulse skew is the absolute difference of the propagation delay times: | t
PLH
– t
PHL
|
45
45
50
50
300
400
55
55
ps
ps
%
%
DC
REF
= 50%
t
r
, t
f
Output Rise/Fall Time 0.1 1.0 ns 0.55 to 2.4 V
