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MPC9443AER2

P1-P3P4-P6P7-P9P10-P12P13-P15
MPC9443
REVISION 6 3/14/16 7 ©2016 Integrated Device Technology, Inc.
MPC9443 Data Sheet 2.5V, 3.3V LVCMOS CLOCK FANOUT BUFFER
Table 11. DC Characteristics (V
CC
= 3.3 V ± 5%, any V
CCA,B,C,D
= 2.5 V ± 5% or 3.3 V ± 5% (mixed), T
A
= –40 to +85°C)
Symbol Characteristics Min Typ Max Unit Condition
V
IH
Input High Voltage 2.0 V
CC
+ 0.3 V LVCMOS
V
IL
Input Low Voltage –0.3 0.8 V LVCMOS
I
IN
Input Current
(1)
1. Input pull-up / pull-down resistors influence input current.
200 A
V
OH
Output High Voltage 2.5 V output
3.3 V output
1.7
2.0
V I
OH
= –15 mA
(2)
I
OH
= 24 mA
(2)
2. The MPC9443 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to
a termination voltage of V
TT
. Alternatively, the device drives up to two 50 series terminated transmission lines
(for V
CC
= 3.3 V) or one 50 series terminated transmission line (for V
CC
=2.5 V).
V
OL
Output Low Voltage 2.5 V output
3.3 V output
0.6
0.55
V I
OL
= 15 mA
(2)
I
OL
= 24 mA
(2)
V
PP
Peak-to-Peak Input Voltage PCLK0,1 250 mV LVPECL
V
CMR
(3)
3. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range and the input
swing lies within the V
PP
(DC) specification.
Common Mode Range PCLK0, 1 1.1 V
CC
– 0.6 V LVPECL
Z
OUT
Output Impedance 2.5 V output
3.3 V output
22
19
C
PD
Power Dissipation Capacitance 10 pF Per Output
I
CCQ
(4)
4. I
CCQ
is the DC current consumption of the device with all outputs open and the input in its default state or open.
Maximum Quiescent Supply Current 3.0 mA All V
CC
Pins
Table 12. AC Characteristics (V
CC
= 3.3 V ± 5%, any V
CCA,B,C,D
= 2.5 V ± 5% or 3.3 V ± 5% (mixed), T
A
= –40 to +85°C)
(1)
(2)
1. AC characteristics apply for parallel output termination of 50 to V
TT
.
2. This table only specifies AC parameter in mixed voltage supply conditions that vary from the corresponding AC tables. For all other parameters, see
Table 8 (for 3.3 V outputs) or Table 10 (for 2.5 V outputs).
Symbol Characteristics Min Typ Max Unit Condition
t
sk(LH, HL)
Output-to-Output Skew
(3)
Any output, same output divider
Any output, any output divider
3. t
sk(LH, HL)
includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge.
275
350
ps
ps
t
sk(PP)
Device-to-Device Skew See Table 8 (3.3 V AC Characteristics)
t
PLH, HL
Propagation Delay See Table 8 (3.3 V AC Characteristics)
t
SK(P)
DC
Q
Output Pulse Skew
(4)
Using PCLK0,1
Using CCLK
Output Duty Cycle f
Q
<140 MHz and using CCLK
f
Q
<250 MHz and using PCLK0,1
4. Output pulse skew is the absolute difference of the propagation delay times: | t
PLH
– t
PHL
|.
45
45
50
50
400
500
55
55
ps
ps
%
%
DC
REF
= 50%
MPC9443
REVISION 6 3/14/16 8 ©2016 Integrated Device Technology, Inc.
MPC9443 Data Sheet 2.5V, 3.3V LVCMOS CLOCK FANOUT BUFFER
APPLICATIONS INFORMATION
Driving Transmission Lines
The MPC9443 clock driver was designed to drive high-speed
signals in a terminated transmission line environment. To provide
the optimum flexibility to the user, the output drivers were
designed to exhibit the lowest impedance possible. With an output
impedance of less than 20  the drivers can drive either parallel
or series terminated transmission lines at V
CC
= 3.3 V. For more
information on transmission lines, the reader is referred to
Freescale application note AN1091. In most high performance
clock networks, point-to-point distribution of signals is the method
of choice. In a point-to-point scheme, either series terminated or
parallel terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a 50
resistance to V
CC
2.
This technique draws a fairly high level of DC current ,and thus,
only a single terminated line can be driven by each output of the
MPC9443 clock driver. For the series terminated case, however,
there is no DC current draw; thus, the outputs can drive multiple
series terminated lines. Figure 3 illustrates an output driving a
single series terminated line versus two series terminated lines in
parallel. When taken to its extreme, the fanout of the MPC9443
clock driver is effectively doubled due to its capability to drive
multiple lines (at V
CC
= 3.3 V).
Figure 3. Single versus Dual Transmission Lines
The waveform plots in Figure 4 show the simulation results of
an output driving a single line versus two lines. In both cases, the
drive capability of the MPC9443 output buffer is more than
sufficient to drive 50 transmission lines on the incident edge.
Note from the delay measurements in the simulations, a delta of
only 43 ps exists between the two differently loaded outputs. This
suggests that the dual line driving need not be used exclusively to
maintain the tight output-to-output skew of the MPC9443. The
output waveform in Figure 4 shows a step in the waveform. This
step is caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 31 series resistor, plus
the output impedance, does not match the parallel combination of
the line impedances. The voltage wave launched down the two
lines will equal:
V
L
=V
S
(Z
0
(R
S
+ R
0
+ Z
0
))
Z
0
=50 || 50
R
S
=31 || 31
R
0
= 19
V
L
= 3.0 (25 (15.5 + 19 + 25)
=1.26 V
At the load end, the voltage will double, due to the near unity
reflection coefficient, to 2.52 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in this
case 4.0 ns).
Figure 4. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the situation in
Figure 5 should be used. In this case, the series terminating
resistors are reduced such that when the parallel combination is
added to the output buffer impedance, the line impedance is
perfectly matched.
Figure 5. Optimized Dual Line Termination
19
IN
MPC9443
Output
Buffer
R
S
= 31
Z
O
= 50
OutA
19
IN
MPC9443
Output
Buffer
R
S
= 31
Z
O
= 50
OutB0
R
S
= 31
Z
O
= 50
OutB1
Time (ns)
Voltage (V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2 4 6 8 10 12 14
OutB
t
D
= 3.9386
OutA
t
D
= 3.8956
In
19
MPC9443
Output
Buffer
R
S
= 12
Z
O
= 50
R
S
= 12
Z
O
= 50
19+ 12 || 12 = 50 || 50
25 = 25
MPC9443
REVISION 6 3/14/16 9 ©2016 Integrated Device Technology, Inc.
MPC9443 Data Sheet 2.5V, 3.3V LVCMOS CLOCK FANOUT BUFFER
Power Consumption of the MPC9443
and Thermal Management
The MPC9443 AC specification is guaranteed for the entire
operating frequency range up to 350 MHz. The MPC9443 power
consumption and the associated long-term reliability may
decrease the maximum frequency limit, depending on operating
conditions such as clock frequency, supply voltage, output
loading, ambient temperature, vertical convection and thermal
conductivity of package and board. This section describes the
impact of these parameters on the junction temperature and gives
a guideline to estimate the MPC9443 die junction temperature
and the associated device reliability. For a complete analysis of
power consumption as a function of operating conditions and
associated long term device reliability, please refer to the
Freescale application note AN1545. According the AN1545, the
long-term device reliability is a function of the die junction
temperature.
Increased power consumption will increase the die junction
temperature and impact the device reliability (MTBF). According
to the system-defined tolerable MTBF, the die junction
temperature of the MPC9443 needs to be controlled, and the
thermal impedance of the board/package should be optimized.
The power dissipated in the MPC9443 is represented in Equation
1.
Where I
CCQ
is the static current consumption of the MPC9443,
C
PD
is the power dissipation capacitance per output. C
L
represents the external capacitive output load, and N is the
number of active outputs (N is always 16 in case of the
MPC9443). The MPC9443 supports driving transmission lines to
maintain high signal integrity and tight timing parameters. Any
transmission line will hide the lumped capacitive load at the end of
the board trace; therefore,
C
L
is zero for controlled transmission
line systems and can be eliminated from Equation 1. Using
parallel termination output termination results in Equation 2 for
power dissipation.
In Equation 2, P stands for the number of outputs with a parallel
or thevenin termination. V
OL
, I
OL
, V
OH
and I
OH
are a function of
the output termination technique, and DC
Q
is the clock signal duty
cycle. If transmission lines are used,
C
L
is zero in Equation 2
and can be eliminated. In general, the use of controlled
transmission line techniques eliminates the impact of the lumped
capacitive loads at the end lines and greatly reduces the power
dissipation of the device. Equation 3 describes the die junction
temperature (T
J)
as a function of the power consumption.
Where R
thja
is the thermal impedance of the package (junction
to ambient), and T
A
is the ambient temperature. According to
Table 13, the junction temperature can be used to estimate the
long-term device reliability. Further, combining Equation 1 and
Equation 2 results in a maximum operating frequency for the
MPC9443 in a series terminated transmission line system.
T
J,MAX
should be selected according to the MTBF system
requirements and Table 13. R
thja
can be derived from
Table 14. The R
thja
represent data based on 1S2P boards. Using
2S2P boards will result in a lower thermal impedance than
indicated below.
If the calculated maximum frequency is below 250 MHz, it
becomes the upper clock speed limit for the given application
conditions. The following eight derating charts describe the safe
frequency operation range for the MPC9443. The charts were
calculated for a maximum tolerable die junction temperature of
110C (120C), corresponding to an estimated MTBF of 9.1 years
(4 years), a supply voltage of 3.3 V and series terminated
transmission line or capacitive loading. Depending on a given set
of these operating conditions and the available device convection
a decision on the maximum operating frequency can be made.
Table 13. Die Junction Temperature and MTFBF
Junction Temperature (C) MTBF (Years)
100 20.4
110 9.1
120 4.2
130 2.0
Table 14. Thermal Package Impedance of the 48 ld LQFP
Convection,
LFPM
R
thja
(1P2S board),
K/W
R
thja
(2P2S board),
K/W
Still air 69 53
100 lfpm
200 lfpm 64 50
300 lfpm
400 lfpm
500 lfpm
P
TOT
= [ I
CCQ
+ V
CC
· f
CLOCK
· ( N · C
PD
+ C
L
) ] · V
CC
M
P
TOT
= V
CC
· [ I
CCQ
+ V
CC
· f
CLOCK
· ( N · C
PD
+ C
L
) ] + [ DC
Q
· I
OH
· (V
CC
– V
OH
) + (1 – DC
Q
) · I
OL
· V
OL
]
MP
T
J
= T
A
+ P
TOT
· R
thja
f
CLOCK,MAX
=
C
PD
· N · V
2
CC
1
· [
– (I
CCQ
· V
CC
) ]
R
thja
T
j,MAX
– T
A
Equation 1
Equation 2
Equation 3
Equation 4
P1-P3P4-P6P7-P9P10-P12P13-P15

MPC9443AER2

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Clock Drivers & Distribution FSL 1-16 LVCMOS Fanout Buffer
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