ADE7769
Rev. A | Page 12 of 20
V2P
V2N
C
F
PHASENEUTRAL
R
F
±165mV
C
F
R
F
R
B
R
A
*
*R
A
>> R
B
+ R
F
05332-010
Figure 20. Typical Connections for Channel V2
POWER SUPPLY MONITOR
The ADE7769 contains an on-chip power supply monitor. The
power supply (V
DD
) is continuously monitored by the ADE7769.
If the supply is less than 4 V, the ADE7769 becomes inactive.
This is useful to ensure proper device operation at power-up
and power-down. The power supply monitor has built-in
hysteresis and filtering, which provide a high degree of
immunity to false triggering from noisy supplies.
In
Figure 21, the trigger level is nominally set at 4 V. The toler-
ance on this trigger level is within ±5%. The power supply and
decoupling for the part should be such that the ripple at V
DD
does not exceed 5 V ± 5%, as specified for normal operation.
V
DD
5V
4V
0V
TIME
INACTIVE ACTIVE INACTIVE
INTERNAL
A
CTIVATION
05332-011
Figure 21. On-Chip Power Supply Monitor
HPF and Offset Effects
Figure 22 shows the effect of offsets on the real power calcula-
tion. As can be seen, offsets on Channel V1 and Channel V2
contribute a dc component after multiplication. Because this dc
component is extracted by the LPF and used to generate the real
power information, the offsets contribute a constant error to the
real power calculation. This problem is easily avoided by the
built-in HPF in Channel V1. By removing the offsets from at
least one channel, no error component can be generated at dc
by the multiplication. Error terms at the line frequency (ω) are
removed by the LPF and the digital-to-frequency conversion
(see the
Digital-to-Frequency Conversion section).
Equation 6 shows how the power calculation is affected by the
dc offsets in the current and voltage channels.
(
)
(
)
}cos{}cos{
OSOS
IωtIVωtV +
×
+
(6)
() ()
ωtVIωtIVIV
IV
OSOSOSOS
coscos
2
×+×+×+
×
=
()
ωt
IV
2cos
2
×
×
+
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
I
OS
× V
V
OS
× I
OS
× I
OS
V × I
2
0
FREQUENCY (RAD/s)
05332-012
Figure 22. Effect of Channel Offset on the Real Power Calculation
The HPF in Channel V1 has an associated phase response that
is compensated for on chip.
Figure 23 and Figure 24 show the
phase error between channels with the compensation network
activated. The ADE7769 is phase compensated up to 1 kHz as
shown. This ensures correct active harmonic power calculation
even at low power factors.
FREQUENCY (Hz)
0.30
PHASE (Degrees)
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
0 100 200 300 400 500 600 700 800 900 1000
05332-013
Figure 23. Phase Error Between Channels (0 Hz to 1 kHz)
ADE7769
Rev. A | Page 13 of 20
FREQUENCY (Hz)
0.30
PHASE (Degrees)
0.25
0.20
0.15
0.10
0.05
0
0.05
0.10
40 45 50 55 60 65 70
05332-014
Figure 24. Phase Error Between Channels (40 Hz to 70 Hz)
Digital-to-Frequency Conversion
As previously described, the digital output of the low-pass
filter after multiplication contains the real power information.
However, because this LPF is not an ideal brick wall filter
implementation, the output signal also contains attenuated
components at the line frequency and its harmonics, that is,
cos(h
ωt) where h = 1, 2, 3, … and so on.
The magnitude response of the filter is given by
()
2
2
45.4
1
1
f
fH
+
=
(7)
For a line frequency of 50 Hz, this gives an attenuation of
the 2
ω (100 Hz) component of approximately 22 dB. The
dominating harmonic is twice the line frequency (2
ω) due to
the instantaneous power calculation.
Figure 25 shows the instantaneous real power signal at the
output of the LPF that still contains a significant amount of
instantaneous power information, that is, cos(2
ωt). This
signal is then passed to the digital-to-frequency converter
where it is integrated (accumulated) over time to produce an
output frequency. The accumulation of the signal suppresses or
averages out any non-dc components in the instantaneous real
power signal. The average value of a sinusoidal signal is zero.
Thus, the frequency generated by the ADE7769 is proportional
to the average real power.
Figure 25 shows the digital-to-
frequency conversion for steady load conditions, that is,
constant voltage and current.
F1
F2
DIGITAL-TO-
FREQUENCY
CF
DIGITAL-TO-
FREQUENCY
MULTIPLIER
F1
TIME
CF
TIME
FREQUENCY FREQUENCY
V
I
0
FREQUENCY (RAD/s)
ω
2ω
COS (2ω)
ATTENUATED BY LPF
V × I
2
LPF TO EXTRACT
REAL POWER
(DC TERM)
INSTANTANEOUS REAL POWER SIGNAL
(FREQUENCY DOMAIN)
LPF
05332-015
Figure 25. Real Power-to-Frequency Conversion
In Figure 25, the frequency output, CF, varies over time, even
under steady load conditions. This frequency variation is
primarily due to the cos(2
ωt) component in the instantaneous
real power signal. The output frequency on CF can be up to
2048 times higher than the frequency on F1 and F2. This higher
output frequency is generated by accumulating the instan-
taneous real power signal over a much shorter time while
converting it to a frequency. This shorter accumulation period
means less averaging of the cos(2
ωt) component. Consequently,
some of this instantaneous power signal passes through the
digital-to-frequency conversion. This is not a problem in the
application. Where CF is used for calibration purposes, the
frequency should be averaged by the frequency counter, which
removes any ripple. If CF is being used to measure energy, for
example in a microprocessor based application, the CF output
should also be averaged to calculate power.
Because the F1 and F2 outputs operate at a much lower
frequency, much more averaging of the instantaneous real
power signal is carried out. The result is a greatly attenuated
sinusoidal content and a virtually ripple-free frequency output.
Connecting to a Microcontroller for Energy
Measurement
The easiest way to interface the ADE7769 to a microcontroller
is to use the CF high frequency output with the output
frequency scaling set to 2048 × F1, F2. This is done by setting
SCF = 0 and S0 = S1 = 1 (see
Table 7). With full-scale ac
signals on the analog inputs, the output frequency on CF is
approximately 2.867 kHz.
Figure 26 shows one scheme that
could be used to digitize the output frequency and carry out
the necessary averaging mentioned in the previous section.
ADE7769
Rev. A | Page 14 of 20
CF
TIME
±10%
FREQUENCY
RIPPLE
AVERAGE
FREQUENCY
ADE7769
COUNTER
TIMER
MCU
CF
05332-016
Figure 26. Interfacing the ADE7769 to an MCU
As shown in Figure 26, the frequency output, CF, is connected
to an MCU counter or port. This counts the number of pulses
in a given integration time, which is determined by an MCU
internal timer. The average power proportional to the average
frequency is given by
Time
Counter
PowerAverageFrequencyAverage ==
(8)
The energy consumed during an integration period is given by
CounterTime
Time
Counter
TimePowerAverageEnergy =×=×=
(9)
For the purpose of calibration, this integration time could be
10 seconds to 20 seconds to accumulate enough pulses to
ensure correct averaging of the frequency. In normal operation,
the integration time could be reduced to 1 or 2 seconds,
depending, for example, on the required update rate of a
display. With shorter integration times on the MCU, the
amount of energy in each update may still have some small
amount of ripple, even under steady load conditions. However,
over a minute or more the measured energy has no ripple.
Power Measurement Considerations
Calculating and displaying power information always has some
associated ripple, which depends on the integration period used
in the MCU to determine average power and also on the load.
For example, at light loads, the output frequency may be 10 Hz.
With an integration period of 2 seconds, only about 20 pulses
are counted. The possibility of missing one pulse always exists,
because the ADE7769 output frequency is running asynchro-
nously to the MCU timer. This results in a 1-in-20, or 5%, error
in the power measurement.
INTERNAL OSCILLATOR (OSC)
The nominal internal oscillator frequency is 450 kHz when
used with RCLKIN, with a nominal value of 6.2 kΩ. The
frequency outputs are directly proportional to the oscillator
frequency, thus RCLKIN must have low tolerance and low
temperature drift to ensure stability and linearity of the chip.
The oscillator frequency is inversely proportional to the
RCLKIN, as shown in
Figure 27. Although the internal
oscillator operates when used with RCLKIN values between
5.5 kΩ and 20 kΩ, choosing a value within the range of the
nominal value, as shown in
Figure 27, is recommended.
RESISTANCE (kΩ)
5.8 5.9 6.1 6.3 6.7
FREQUENCY (kHz)
420
430
440
450
460
480
470
490
6.0 6.2 6.4 6.5 6.6
410
400
05332-017
Figure 27. Effect of RCLKIN on Internal Oscillator Frequency (OSC)
TRANSFER FUNCTION
Frequency Outputs F1 and F2
The ADE7769 calculates the product of two voltage signals
(on Channel V1 and Channel V2) and then low-pass filters this
product to extract real power information. This real power
information is then converted to a frequency. The frequency
information is output on F1 and F2 in the form of active low
pulses. The pulse rate at these outputs is relatively low, for
example, 0.175 Hz maximum for ac signals with S0 = S1 = 0
(see
Table 6). This means that the frequency at these outputs is
generated from real power information accumulated over a
relatively long period of time. The result is an output frequency
that is proportional to the average real power. The averaging of
the real power signal is implicit to the digital-to-frequency
conversion. The output frequency or pulse rate is related to the
input voltage signals by the following equation:
2
75.494
REF
41
rmsrms
V
FV2V1
Freq
×
×
×
=
(10)
where:
Freq is the output frequency on F1 and F2 (Hz).
V1
rms
is the differential rms voltage signal on Channel V1 (V).
V2
rms
is the differential rms voltage signal on Channel V2 (V).
V
REF
= is the reference voltage (2.45 V ± 200 mV) (V).
F
1–4
= are one of four possible frequencies selected by using
the S0 and S1logic inputs (see
Table 5).

ADE7769ARZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized Energy Meter IC w/ Intg Oscillator
Lifecycle:
New from this manufacturer.
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