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P89LPC925FN,129

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P49
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data Rev. 03 — 15 December 2004 19 of 49
9397 750 14471
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.9.2 Features
• 8-bit, 4-channel multiplexed input, successive approximation A/D converter.
• Four result registers.
• Six operating modes
– Fixed channel, single conversion mode
– Fixed channel, continuous conversion mode
– Auto scan, single conversion mode
– Auto scan, continuous conversion mode
– Dual channel, continuous conversion mode
– Single step mode
• Three conversion start modes
– Timer triggered start
– Start immediately
– Edge triggered
• 8-bit conversion time of ≥ 3.9 µs at an ADC clock of 3.3 MHz
• Interrupt or polled operation
• Boundary limits interrupt
• DAC output to a port pin with high output impedance
• Clock divider
• Power down mode
8.9.3 A/D operating modes
Fixed channel, single conversion mode: A single input channel can be selected for
conversion. A single conversion will be performed and the result placed in the result
register which corresponds to the selected input channel. An interrupt, if enabled, will
be generated after the conversion completes.
Fixed channel, continuous conversion mode: A single input channel can be
selected for continuous conversion. The results of the conversions will be sequentially
placed in the four result registers. An interrupt, if enabled, will be generated after
every four conversions. Additional conversion results will again cycle through the four
result registers, overwriting the previous results. Continuous conversions continue
until terminated by the user.
Auto scan, single conversion mode: Any combination of the four input channels
can be selected for conversion. A single conversion of each selected input will be
performed and the result placed in the result register which corresponds to the
selected input channel. An interrupt, if enabled, will be generated after all selected
channels have been converted. If only a single channel is selected this is equivalent
to single channel, single conversion mode.
Auto scan, continuous conversion mode: Any combination of the four input
channels can be selected for conversion. A conversion of each selected input will be
performed and the result placed in the result register which corresponds to the
selected input channel. An interrupt, if enabled, will be generated after all selected
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data Rev. 03 — 15 December 2004 20 of 49
9397 750 14471
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
channels have been converted. The process will repeat starting with the first selected
channel. Additional conversion results will again cycle through the four result
registers, overwriting the previous results. Continous conversions continue until
terminated by the user.
Dual channel, continuous conversion mode: This is a variation of the auto scan
continuous conversion mode where conversion occurs on two user-selectable inputs.
The result of the conversion of the first channel is placed in result register, AD1DAT0.
The result of the conversion of the second channel is placed in result register,
AD1DAT1. The first channel is again converted and its result stored in AD1DAT2. The
second channel is again converted and its result placed in AD1DAT3. An interrupt is
generated, if enabled, after every set of four conversions (two conversions per
channel).
Single step mode: This special mode allows ‘single-stepping’ in an auto scan
conversion mode. Any combination of the four input channels can be selected for
conversion. After each channel is converted, an interrupt is generated, if enabled,
and the A/D waits for the next start condition. May be used with any of the start
modes.
8.9.4 Conversion start modes
Timer triggered start: An A/D conversion is started by the overflow of Timer 0. Once
a conversion has started, additional Timer 0 triggers are ignored until the conversion
has completed. The Timer triggered start mode is available in all A/D operating
modes.
Start immediately: Programming this mode immediately starts a conversion. This
start mode is available in all A/D operating modes.
Edge triggered: An A/D conversion is started by rising or falling edge of P1.4. Once
a conversion has started, additional edge triggers are ignored until the conversion
has completed. The edge triggered start mode is available in all A/D operating
modes.
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data Rev. 03 — 15 December 2004 21 of 49
9397 750 14471
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.9.5 Boundary limits interrupt
The A/D converter has both a high and low boundary limit register. After the four
MSBs have been converted, these four bits are compared with the four MSBs of the
boundary high and low registers. If the four MSBs of the conversion are outside the
limit an interrupt will be generated, if enabled. If the conversion result is within the
limits, the boundary limits will again be compared after all 8 bits have been converted.
An interrupt will be generated, if enabled, if the result is outside the boundary limits.
The boundary limit may be disabled by clearing the boundary limit interrupt enable.
8.9.6 DAC output to a port pin with high output impedance
The A/D converter’s DAC block can be output to a port pin. In this mode, the
AD1DAT3 register is used to hold the value fed to the DAC. After a value has been
written to the DAC, the DAC output will appear on the channel 3 pin.
8.9.7 Clock divider
The A/D converter requires that its internal clock source be in the range of 500 kHz to
3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock
from 1 to 8 is provided for this purpose.
8.9.8 Power-down and idle mode
In idle mode the A/D converter, if enabled, will continue to function and can cause the
device to exit idle mode when the conversion is completed if the A/D interrupt is
enabled. In Power-down mode or Total power-down mode, the A/D does not function.
If the A/D is enabled, it will consume power. Power can be reduced by disabling the
A/D.
8.10 Memory organization
The various P89LPC924/925 memory spaces are as follows:
• DATA
128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect
addressing, using instruction other than MOVX and MOVC. All or part of the Stack
may be in this area.
• IDATA
Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of
the Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it.
• SFR
Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing.
• CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC924/925 has 4 kB/8 kB of on-chip Code memory.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P49

P89LPC925FN,129

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Buy P89LPC925FN,129
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 8KB FLASH 20DIP
Lifecycle:
New from this manufacturer.
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