OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

P89LPC925FN,129

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P49
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data Rev. 03 — 15 December 2004 25 of 49
9397 750 14471
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Digital outputs are disabled by putting the port output into the Input-Only (high
impedance) mode as described in Section 8.13.4.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register,
bits 1:5. On any reset, PT0AD1:5 defaults to ‘0’s to enable digital functions.
8.13.7 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different
from the LPC76x series of devices.
• After power-up, all I/O pins except P1.5, may be configured by software.
• Pin P1.5 is input only. Pins P1.2 and P1.3 and are configurable for either input-only
or open-drain.
Every output on the P89LPC924/925 has been designed to sink typical LED drive
current. However, there is a maximum total output current for all ports which must not
be exceeded. Please refer to Table 8 “DC electrical characteristics” for detailed
specifications.
All ports pins that can function as an output have slew rate controlled outputs to limit
noise generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
8.14 Power monitoring functions
The P89LPC924/925 incorporates power monitoring functions designed to prevent
incorrect operation during initial power-up and power loss or reduction during
operation. This is accomplished with two hardware functions: Power-on Detect and
Brownout detect.
8.14.1 Brownout detection
The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor
reset, however it may alternatively be configured to generate an interrupt.
Brownout detection may be enabled or disabled in software.
If Brownout detection is enabled, the brownout condition occurs when V
DD
falls below
the brownout trip voltage, V
BO
(see Table 8 “DC electrical characteristics”), and is
negated when V
DD
rises above V
BO
. If the P89LPC924/925 device is to operate with
a power supply that can be below 2.7 V, BOE should be left in the unprogrammed
state so that the device can operate at 2.4 V, otherwise continuous brownout reset
may prevent the device from operating.
For correct activation of Brownout detect, the V
DD
rise and fall times must be
observed. Please see Table 8 “DC electrical characteristics” for specifications.
8.14.2 Power-on detection
The Power-on Detect has a function similar to the Brownout detect, but is designed to
work as power comes up initially, before the power supply voltage reaches a level
where Brownout detect can work. The POF flag in the RSTSRC register is set to
indicate an initial power-up condition. The POF flag will remain set until cleared by
software.
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data Rev. 03 — 15 December 2004 26 of 49
9397 750 14471
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.15 Power reduction modes
The P89LPC924/925 supports three different power reduction modes. These modes
are Idle mode, Power-down mode, and total Power-down mode.
8.15.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate
Idle mode.
8.15.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption.
The P89LPC924/925 exits Power-down mode via any reset, or certain interrupts. In
Power-down mode, the power supply voltage may be reduced to the RAM keep-alive
voltage V
RAM
. This retains the RAM contents at the point where Power-down mode
was entered. SFR contents are not guaranteed after V
DD
has been lowered to V
RAM
,
therefore it is highly recommended to wake up the processor via reset in this case.
V
DD
must be raised to within the operating range before the Power-down mode is
exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down. These include: Brownout detect,
Watchdog Timer, Comparators (note that Comparators can be powered-down
separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is
disabled unless both the RC oscillator has been selected as the system clock AND
the RTC is enabled.
8.15.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry
and the voltage comparators are also disabled to conserve additional power. The
internal RC oscillator is disabled unless both the RC oscillator has been selected as
the system clock and the RTC is enabled. If the internal RC oscillator is used to clock
the RTC during Power-down, there will be high power consumption. Please use an
external low frequency clock to achieve low power with the Real-Time Clock running
during Power-down.
8.16 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital
input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the
external reset input function on P1.5. When cleared, P1.5 may be used as an input
pin.
Remark: During a power-up sequence, the RPE selection is overridden and this pin
will always function as a reset input. An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset. After power-up this input will function either as an external reset
input or as a digital input as defined by the RPE bit. Only a power-up reset will
temporarily override the selection defined by RPE bit. Other sources of reset will not
override the RPE bit.
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data Rev. 03 — 15 December 2004 27 of 49
9397 750 14471
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Remark: During a power cycle, V
DD
must fall below V
POR
(see Table 8 “DC electrical
characteristics” on page 40) before power is reapplied, in order to ensure a power-on
reset.
Reset can be triggered from the following sources:
• External reset pin (during power-up or if user configured via UCFG1. This option
must be used for an oscillator frequency above 12 MHz);
• Power-on detect;
• Brownout detect;
• Watchdog Timer;
• Software reset;
• UART break character detect reset.
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can
read this register to determine the most recent reset source. These flag bits can be
cleared in software by writing a ‘0’ to the corresponding bit. More than one flag bit
may be set:
• During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
• For any other reset, previously set flag bits that have not been cleared will remain
set.
8.16.1 Reset vector
Following reset, the P89LPC924/925 will fetch instructions from either address 0000h
or the Boot address. The Boot address is formed by using the Boot Vector as the high
byte of the address and the low byte of the address = 00h.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on
(see
P89LPC924/925 User’s Manual
). Otherwise, instructions will be fetched from
address 0000H.
8.17 Timers/counters 0 and 1
The P89LPC924/925 has two general purpose counter/timers which are upward
compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to
operate either as timers or event counter. An option to automatically toggle the T0
and/or T1 pins upon timer overflow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition
at its corresponding external input pin, T0 or T1. In this function, the external input is
sampled once during every machine cycle.
Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1,
2 and 6 are the same for both Timers/Counters. Mode 3 is different.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P49

P89LPC925FN,129

Mfr. #:
Buy P89LPC925FN,129
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 8KB FLASH 20DIP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet