Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data Rev. 03 — 15 December 2004 34 of 49
9397 750 14471
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.21.2 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag
is set whenever the comparator output changes state. The flag may be polled by
software or may be used to generate an interrupt. The two comparators use one
common interrupt vector. If both comparators enable interrupts, after entering the
interrupt service routine, the user needs to read the flags to determine which
comparator caused the interrupt.
8.21.3 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is
activated, but both comparators are disabled automatically in Total Power-down
mode. If a comparator interrupt is enabled (except in Total Power-down mode), a
change of the comparator output state will generate an interrupt and wake up the
processor. If the comparator output to a pin is enabled, the pin should be configured
in the push-pull mode in order to obtain fast switching times while in Power-down
mode. The reason is that with the oscillator stopped, the temporary strong pull-up that
normally occurs during switching on a quasi-bidirectional port pin does not take
place.
Comparators consume power in Power-down and Idle modes, as well as in the
normal operating mode. This fact should be taken into account when system power
consumption is an issue. To minimize power consumption, the user can disable the
comparators via PCONA.5, or put the device in Total Power-down mode.
8.22 Keypad interrupt (KBI)
The Keypad Interrupt function is intended primarily to allow a single interrupt to be
generated when Port 0 is equal to or not equal to a certain pattern. This function can
be used for bus address recognition or keypad recognition. The user can configure
the port via SFRs for different tasks.
The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins
connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN)
is used to define a pattern that is compared to the value of Port 0. The Keypad
Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when
the condition is matched while the Keypad Interrupt function is active. An interrupt will
be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register
(KBCON) is used to define equal or not-equal for the comparison.
In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x
series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then
any key connected to Port 0 which is enabled by the KBMASK register will cause the
hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt
may be used to wake up the CPU from Idle or Power-down modes. This feature is
particularly useful in handheld, battery-powered systems that need to carefully
manage power consumption yet also need to be convenient to use.
In order to set the flag and cause an interrupt, the pattern on Port 0 must be held
longer than 6 CCLKs.
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data Rev. 03 — 15 December 2004 35 of 49
9397 750 14471
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.23 Watchdog timer
The watchdog timer causes a system reset when it underflows as a result of a failure
to feed the timer prior to the timer reaching its terminal count. It consists of a
programmable 12-bit prescaler, and an 8-bit down counter. The down counter is
decremented by a tap taken from the prescaler. The clock source for the prescaler is
either the PCLK or the nominal 400 kHz Watchdog oscillator. The watchdog timer can
only be reset by a power-on reset. When the watchdog feature is disabled, it can be
used as an interval timer and may generate an interrupt. Figure 11 shows the
watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte
sequence. If PCLK is selected as the watchdog clock and the CPU is powered-down,
the watchdog is disabled. The watchdog timer has a time-out period that ranges from
a few µs to a few seconds. Please refer to the
P89LPC924/925
User’s Manual for
more details.
8.24 Additional features
8.24.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor
completely, as if an external reset or watchdog reset had occurred. Care should be
taken when writing to AUXR1 to avoid accidental software resets.
8.24.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects
one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so
that the DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of inadvertently altering other
bits in the register.
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
feed sequence.
Fig 11. Watchdog timer in Watchdog mode (WDTE = ‘1’).
PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK
WDCON (A7H)
CONTROL REGISTER
PRESCALER
002aaa423
SHADOW
REGISTER
FOR WDCON
8-BIT DOWN
COUNTER
WDL (C1H)
Watchdog
oscillator
PCLK
÷32
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
RESET
see note (1)
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data Rev. 03 — 15 December 2004 36 of 49
9397 750 14471
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.25 Flash program memory
8.25.1 General description
The P89LPC924/925 Flash memory provides in-circuit electrical erasure and
programming. The Flash can be read, erased, or written as bytes. The Sector and
Page Erase functions can erase any Flash sector (1 kB) or page (64 bytes). The Chip
Erase operation will erase the entire program memory. In-System Programming and
standard parallel programming are both available. On-chip erase and write timing
generation contribute to a user-friendly programming interface. The P89LPC924/925
Flash reliably stores memory contents even after 100,000 erase and program cycles.
The cell is designed to optimize the erase and programming mechanisms. The
P89LPC924/925 uses V
DD
as the supply voltage to perform the Program/Erase
algorithms.
8.25.2 Features
Parallel programming with industry-standard commercial programmers.
In-Circuit serial Programming (ICP) with industry-standard commercial
programmers.
IAP-Lite allows individual and multiple bytes of code memory to be used for data
storage and programmed under control of the end application.
Internal fixed boot ROM, containing low-level In-Application Programming (IAP)
routines that can be called from the end application (in addition to IAP-Lite).
Default serial loader providing In-System Programming (ISP) via the serial port,
located in upper end of user program memory.
Boot vector allows user-provided Flash loader code to reside anywhere in the
Flash memory space, providing flexibility to the user.
Programming and erase over the full operating voltage range.
Read/Programming/Erase using ISP/IAP/IAP-Lite.
Any flash program operation in 2 ms.
Any flash erase operation in 4 ms.
Programmable security for the code in the Flash for each sector.
>100,000 typical erase/program cycles for each byte.
10 year minimum data retention.
8.25.3 ISP and IAP capabilities of the P89LPC924/925
Flash organization: The P89LPC924/925 program memory consists of four/eight
1 kB sectors. Each sector can be further divided into 64-byte pages. In addition to
sector erase, page erase, and byte erase, a 64-byte page register is included which
allows from 1 to 64 bytes of a given page to be programmed at the same time,
substantially reducing overall programming time. An In-Application Programming
(IAP) interface is provided to allow the end user’s application to erase and reprogram
the user code memory. In addition, erasing and reprogramming of
user-programmable bytes including UCFG1, the Boot Status Byte and the Boot
Vector are supported. As shipped from the factory, the upper 512 bytes of user code
space contains a serial In-System Programming (ISP) routine allowing for the device
to be programmed in circuit through the serial port.

P89LPC925FN,129

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 8KB FLASH 20DIP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union